Vertical Semiconductor Channel Nitrogen Profile
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Solution Overview
Problem
Conventional memory devices with planar transistor structures face limitations in integrity and performance as memory density increases, prompting the need for alternative vertical transistor structures to enhance memory device capabilities.
Innovation Solution
A semiconductor device with a vertical structure featuring a channel region extending perpendicular to the substrate, comprising a first semiconductor layer with a nitrogen concentration distribution, gate electrodes on the side wall, and a gate dielectric layer, along with a method of manufacturing involving in-situ doping and nitridation processes to achieve specific nitrogen concentration profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a planar transistor structure is used in conventional memory devices, then the device structure is simple and easy to manufacture, but the memory integrity and performance deteriorate as memory density increases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor structure by extending the channel region perpendicular to the substrate surface. This dimensional change allows the channel to stand vertically rather than lying flat, enabling improved memory integrity and performance while accommodating higher memory density requirements.
Solution Approach 2:
The patent introduces nitrogen concentration distribution as a key parameter to control trap density in the channel region. By varying the nitrogen concentration profile (higher near the gate dielectric interface and lower in the bulk), the device optimizes electrical characteristics including reduced threshold voltage shift and improved on-current, thereby enhancing memory reliability.
2Reliability
If nitrogen concentration is increased near the gate dielectric interface to reduce trap density, then electrical characteristics improve, but the manufacturing precision required to control nitrogen distribution increases
Solution Approach 1:
The patent incorporates nitrogen atoms into the channel region during the in-situ formation of the semiconductor layer, before subsequent processing steps. This preliminary doping action establishes the desired nitrogen concentration profile early in the manufacturing process, reducing the need for additional precision-critical nitrogen adjustment steps later.
Solution Approach 2:
The patent replaces traditional ion implantation or diffusion methods with in-situ doping during chemical vapor deposition. This substitution allows for more precise and uniform nitrogen concentration control directly during layer formation, reducing manufacturing complexity while achieving the desired trap density reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical structure with nitrogen concentration distribution reduces trap density and improves electrical characteristics, such as increased on-current and reduced threshold voltage shift, enhancing the performance and reliability of memory devices.
Implementation Method 1
forming a first semiconductor layer on the opening with an in-situ doping of nitrogen atoms at a first concentration
Implementation Method 2
a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution
Data Source
AI summary
A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.