Vertical Channel Non-Volatile Memory Leakage Control
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Solution Overview
Problem
Current non-volatile memory devices face challenges in increasing integration density and performance within a limited area, particularly in effectively disconnecting vertical channels from the well during programming and read operations to prevent leakage current, and in efficiently erasing memory cells.
Innovation Solution
A non-volatile memory device design featuring a substrate with a well, first and second vertical channels, and a pipe channel connecting them, along with a cut-off gate electrode and a pipe gate electrode, which allows for electrical disconnection during programming and read operations and connection during erase operations, utilizing a layered structure with interlayer insulating layers and channel isolation patterns to manage voltage and prevent leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical channels are connected to the well continuously, then device simplicity is maintained, but leakage current occurs during programming and read operations
Solution Approach 1:
The continuous vertical channel is segmented into multiple sections by introducing a cut-off gate electrode that divides the channel into a first vertical channel section and a second vertical channel section. This segmentation allows independent control of different channel portions, enabling leakage prevention during programming and read operations while maintaining simple connectivity during erase operations.
Solution Approach 2:
The cut-off gate electrode is configured to dynamically change the electrical state of the vertical channel between connected and disconnected states. By applying different voltages to the cut-off gate electrode, the channel conductivity can be switched on-demand to prevent leakage current when needed while maintaining connectivity for erase operations.
2Productivity
If memory cells are erased individually, then precision is maintained, but erasure efficiency is reduced
Solution Approach 1:
The vertical channel is divided into multiple independent sections that can be selectively controlled. The first vertical channel section connects to the first memory cell string, the second vertical channel section connects to the second memory cell string, and the pipe channel connects these sections. This segmentation enables block-wise erasure by controlling specific channel sections while maintaining the ability to perform individual cell operations.
Solution Approach 2:
The pipe gate electrode and cut-off gate electrode structure serves multiple functions: it enables both individual memory cell selection and block-wise erasure operations. The same structural elements that provide precise cell addressing also facilitate efficient block erasure by allowing simultaneous control of multiple channel sections.
3Reliability
If integration density is increased, then device performance is improved, but leakage control becomes more difficult
Solution Approach 1:
The solution transitions from planar gate control to vertical stacking of gate electrodes. By stacking the cut-off gate electrode, pipe gate electrode, and memory cell gate electrodes in the vertical dimension, the patent achieves fine-grained control over channel conductivity without increasing lateral device footprint, thus maintaining integration density while improving leakage control.
Solution Approach 2:
The gate electrode structure employs a nested configuration where the cut-off gate electrode surrounds the vertical channel, the pipe gate electrode is positioned above it, and memory cell gate electrodes are stacked above the pipe gate electrode. This nested arrangement allows multiple control functions to be integrated in a compact vertical structure, managing leakage control complexity while maintaining high integration density.
Data Source
AI summary
Provided is a non-volatile memory device having a vertical channel cell. The non-volatile memory device includes a substrate having a well. A first vertical channel and a second vertical channel are in contact with the well, and protrude from the well. A pipe channel connecting the first and second vertical channels is disposed. A cut-off gate electrode stacked over the well, and surrounding side surfaces of the first and second vertical channels is disposed. A pipe gate electrode stacked over the cut-off gate electrode, and having the pipe channel is disposed. A plurality of memory-cell gate electrodes stacked over the pipe gate electrode, and surrounding the side surfaces of the first and second vertical channels is disposed. A select gate electrode stacked over the plurality of memory-cell gate electrodes, and surrounding the side surfaces of the first and second vertical channels is disposed.