3D Memory Vertical Channel On-Current via <110> Orientation
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Solution Overview
Problem
As the number of word lines increases in three-dimensional memory devices, the on-current for vertical semiconductor channels decreases, necessitating a method to enhance on-current and enable vertical scaling while maintaining device density.
Innovation Solution
The use of epitaxial vertical semiconductor channels and specific manufacturing processes, including forming alternating stacks of insulating and sacrificial layers, etching memory openings, and replacing sacrificial material with conductive layers, to create memory stack structures with enhanced charge carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased in three-dimensional memory devices, then device density is improved, but on-current for vertical semiconductor channels decreases
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the semiconductor channel from conventional <100> to <110> orientation. This parameter change fundamentally alters the charge carrier mobility characteristics, enabling higher on-current despite increased device density and more word lines. The <110> orientation provides superior electron transport properties that compensate for the current reduction caused by higher density scaling.
Solution Approach 2:
The patent employs a composite structure combining alternating layers of semiconductor material and sacrificial material, followed by replacement of sacrificial material with conductive material. This creates a composite memory stack with enhanced electrical properties. The composite approach allows optimization of both density (through multiple word lines) and current (through improved material composition and channel structure).
2Quantity of substance
If vertical scaling is performed to increase device density, then quantity of memory cells is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the alternating stack of semiconductor and sacrificial layers before defining the final memory structure. The sacrificial layers are pre-positioned to guide subsequent self-aligned etching processes. This preliminary structuring simplifies the manufacturing of complex 3D vertical channels by establishing a template that directs material deposition and removal in a controlled sequence, reducing overall process complexity despite vertical scaling.
Solution Approach 2:
The patent segments the manufacturing process into distinct modular stages: forming alternating stacks, selective etching of sacrificial layers, depositing conductive materials, and forming vertical channels. This segmentation allows each complex step to be independently optimized and controlled. The modular approach manages manufacturing complexity by breaking down the intricate vertical scaling process into manageable, repeatable units that can be precisely controlled.
3Productivity
If substrate reuse is implemented during manufacture, then productivity is improved, but risk of damaging peripheral circuitry increases
Solution Approach 1:
The patent uses sacrificial layers as intermediary structures that protect the peripheral circuitry during substrate reuse. These sacrificial layers are strategically positioned to shield sensitive areas during etching and material deposition processes. The intermediaries enable aggressive processing needed for high-density vertical structures while preventing damage to peripheral circuits, thus allowing substrate reuse without compromising circuit integrity.
Solution Approach 2:
The patent employs disposable sacrificial layers that are intentionally designed to be removed after serving their protective function. These temporary structures enable aggressive manufacturing processes during substrate reuse by providing a sacrificial buffer that can be discarded. The cheap, removable nature of these layers allows high-productivity processing while protecting valuable peripheral circuitry, as the protective layers are simply removed after serving their purpose.
Data Source
AI summary
A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry. Substrates employed to provide the memory die and the support die can be reused by replacing one of the substrates with an alternative low-cost substrate that provides structural support to the bonded assembly.