Vertical Channel Transistor Structure for Higher On-Current Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing integration, operation speed, and current driving ability, particularly in vertical transistors, where existing designs struggle to optimize performance and reliability.
Innovation Solution
The semiconductor device incorporates a vertical channel structure with specific metal oxide layers, including a channel layer with a first metal oxide, a lower and upper insertion layer with higher bonding energy metal oxides, and source/drain regions with metal dopants and oxygen vacancies, optimized for improved electrical conductivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel transistors are used to expand integration and current driving ability, then device integration and current capacity are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The channel layer is divided into multiple segments with different metal oxide materials (first metal oxide in main channel, second metal oxide in source/drain regions). This segmentation allows optimization of different regions for different functions: the first metal oxide provides high mobility in the channel, while the second metal oxide with higher bonding energy provides stability in source/drain regions, thereby improving overall device performance while managing manufacturing complexity through modular material selection
Solution Approach 2:
The patent employs composite material structure by combining different metal oxides (such as In-Ga-Zn-O with Al-O or Ti-O) in specific spatial arrangements. The composite structure leverages the high electrical conductivity of In-Ga-Zn-O in the channel region while utilizing the higher bonding energy of Al-O or Ti-O in source/drain regions to enhance thermal stability and reduce defect formation, thus improving current driving ability without proportionally increasing manufacturing complexity
2Reliability
If metal oxide layers are used in vertical transistors to improve electrical conductivity, then on-current increases, but device reliability may deteriorate due to lower bonding energy
Solution Approach 1:
Different metal oxide materials are assigned to different spatial regions: the first metal oxide (e.g., In-Ga-Zn-O) with high electrical conductivity is placed in the channel region where high on-current is needed, while the second metal oxide (e.g., Al-O or Ti-O) with higher bonding energy is placed in the source/drain regions where structural stability is critical. This local quality differentiation simultaneously optimizes both electrical conductivity and bonding strength in their respective regions
Solution Approach 2:
The first metal oxide layer acts as an intermediary between the bit line and the channel, providing a transition zone with optimized electrical and mechanical properties. This intermediary layer enables gradual transition of material properties, allowing the device to achieve high on-current through the channel while maintaining overall structural reliability through the buffered interface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the on-current and reliability of vertical transistors, addressing integration and speed limitations by leveraging the higher bonding energy of specific metal oxides and oxygen vacancies for improved electrical conductivity.
Implementation Method 1
the second metal oxide has greater bonding energy than the first metal oxide
Implementation Method 2
A lower source/drain region is provided, which is disposed between the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide
Data Source
AI summary
A vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. A lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. A lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. An upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. An insulated gate line is provided on the channel layer.


