Vertical-Channel Oxide Transistor Layout for Compact Reliable Semiconductors

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving high density integration, reduced size, low power consumption, and high reliability, particularly in transistors using oxide semiconductors with indium and gallium.

Innovation Solution

The semiconductor device is designed with a specific configuration of transistors connected in a manner that allows for efficient signal transmission and low power consumption, utilizing oxide semiconductors with indium and zinc, and insulating layers with silicon and nitrogen, to occupy a small area and enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If transistors are miniaturized to achieve high density integration, then the occupied area is reduced, but the reliability and performance stability deteriorate

Engineering Contradiction:
Improveoccupied areaVSAvoidperformance stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from planar transistors to vertical-channel transistors, changing the channel direction from horizontal to vertical. This dimensional change allows the transistor to achieve high density integration through vertical stacking while maintaining stable performance characteristics through the vertical channel structure that provides better control over the semiconductor layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs oxide semiconductor materials (such as In-Ga-Zn-O) with specific compositional ratios as the semiconductor layer. This composite material approach enables the transistor to achieve both miniaturization and reliable performance by utilizing the unique electrical characteristics of oxide semiconductors that maintain stability even in reduced dimensions.

Inventive Principle:
Principle #40Composite materials

2Reliability

If oxide semiconductor layers are used to improve field-effect mobility, then the manufacturing complexity increases

Engineering Contradiction:
Improvefield-effect mobilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent optimizes the compositional parameters of the oxide semiconductor layer, specifically controlling the atomic ratios of metals (such as In:Ga:Zn = 1:1:1 or 2:1:3) and oxygen content. By precisely controlling these parameters during formation, the patent achieves high field-effect mobility while maintaining manufacturability through standardized process parameters.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The oxide semiconductor layer serves multiple functions simultaneously: it provides the active channel for transistor operation, enables high field-effect mobility through its material properties, and allows for vertical stacking to reduce area. This multi-functionality reduces overall device complexity despite the specialized material requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If vertical-channel transistor structure is adopted to reduce area, then the manufacturing process complexity increases

Engineering Contradiction:
Improveoccupied areaVSAvoidmanufacturing process complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The vertical-channel transistor is segmented into distinct functional layers: gate electrode, gate insulating layer, semiconductor layer, source/drain electrodes, and interlayer insulating layers. This segmentation allows each layer to be formed using standardized deposition and patterning processes, reducing overall manufacturing complexity despite the vertical architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a stacked configuration where multiple transistor layers are vertically nested, with each layer containing gate, semiconductor, and electrode structures. This nesting approach achieves high density integration by stacking functional units vertically while using the same manufacturing processes for each layer, thereby reducing process complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12575132B2Semiconductor device
Publication Date: 2026.03.10 SEMICON ENERGY LAB CO LTD
  • US12575132B2 patent drawing
  • US12575132B2 patent drawing
  • US12575132B2 patent drawing

AI summary

A novel semiconductor device is provided. The semiconductor device is a single-polarity semiconductor device including a vertical-channel transistor. In the vertical-channel transistor, the higher parasitic capacitance value of the gate-source parasitic capacitance and the gate-drain parasitic capacitance is used as a bootstrap capacitor, which decreases the occupied area of the semiconductor device. The use of an oxide semiconductor for a semiconductor layer of the vertical-channel transistor increases the breakdown voltage between the source and the drain, which can shorten the channel length. In addition, stable operation can be performed even in a high-temperature environment.