Vertical Transistor Channel Pad Structure for Higher Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high-capacity data processing while maintaining a reduced volume, requiring an enhanced degree of integration, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device with a vertical transistor structure is proposed, featuring gate electrodes stacked on a substrate, channel structures with a gate dielectric layer and channel pad, and separation regions, where the gate dielectric layer extends beyond the channel layer to contact the channel pad, and includes a connection structure with varying widths to enhance integration and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional coplanar transistor structure is used, then the device structure is simple and easy to manufacture, but the degree of integration is limited and volume cannot be reduced
Solution Approach 1:
The patent transitions from a conventional coplanar (2D) transistor structure to a vertical (3D) transistor structure where the channel extends in the vertical direction through stacked gate electrodes. This dimensional change enables higher degree of integration and reduced device volume while maintaining electrical performance, directly resolving the contradiction between structural simplicity and integration density
2Reliability
If the gate dielectric layer extends upwardly beyond the channel layer, then stable electrical connection and improved reliability are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The gate dielectric layer is formed to extend upwardly beyond the channel layer before the channel pad is deposited. This preliminary extension ensures that when the channel pad is subsequently formed, it automatically makes contact with the gate dielectric layer, guaranteeing stable electrical connection without requiring high-precision alignment during pad formation
Solution Approach 2:
The gate dielectric layer exhibits different heights at different locations: it extends upwardly at the inner side surface where it contacts the channel pad for reliable electrical connection, while maintaining appropriate thickness elsewhere for proper electrical isolation. This localized variation in geometry optimizes both reliability and manufacturability
3Productivity
If the connection structure has varying widths to enhance integration, then electrical characteristics and integration density are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The connection structure is divided into multiple segments with different widths: a first width at the upper end of the lower channel structure, a second width at the lower end of the upper channel structure, and a third width for the connection structure itself. This segmentation allows each portion to be optimized for its specific function while maintaining overall integration density
Solution Approach 2:
The connection structure utilizes varying width parameters (first width, second width, third width) to optimize electrical characteristics and integration density. By changing the geometric parameter of width at different locations, the structure achieves improved performance without requiring fundamentally complex manufacturing processes
Data Source
AI summary
A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.