Vertical Channel Pattern in 3D Semiconductor Memory Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integrity of 2D semiconductor memory devices is limited by the high cost of micronization equipment, which restricts their performance and reliability due to the area occupied by unit memory cells.
Innovation Solution
A semiconductor memory device with a vertical stacking structure comprising insulating layers and gate electrodes on a substrate, featuring a lower semiconductor pattern with a recess region and a vertical channel pattern that increases electron mobility and prevents excessive etching, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 2D semiconductor memory devices use conventional planar structure, then manufacturing process is simpler, but integrity is limited due to area occupied by unit memory cells
Solution Approach 1:
The patent transitions from a conventional 2D planar memory structure to a 3D vertical stacking structure. Multiple memory cells are stacked vertically with alternating insulating layers and gate electrodes, enabling higher density and improved integrity without being constrained by the planar area of individual unit memory cells.
2Reliability
If micronization equipment is used to reduce unit memory cell area, then integrity can be improved, but equipment cost becomes excessively high
Solution Approach 1:
Instead of relying on expensive micronization equipment to shrink 2D unit memory cells, the patent achieves higher density by stacking memory cells vertically in three dimensions. This approach improves integrity through better pattern formation while avoiding the need for costly advanced lithography equipment.
3Reliability
If vertical channel pattern thickness is reduced to improve electron mobility, then electrical characteristics improve, but excessive etching may cause disconnection
Solution Approach 1:
The patent introduces a recess region with a curved profile in the lower semiconductor pattern, creating a localized area that accommodates the vertical channel pattern. This local structural modification allows the channel pattern to maintain optimal thickness for electron mobility while the curved walls provide mechanical support and protection against excessive etching that could cause disconnection.
Data Source
AI summary
A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.