Vertical-Channel Peripheral Circuits for Compact Memory Layouts
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Solution Overview
Problem
The increasing demand for high-performance and multifunctional semiconductor devices necessitates finer patterns and narrower separation distances, posing challenges in manufacturing and integration.
Innovation Solution
The semiconductor device incorporates a peripheral circuit region with transistors having a vertical channel structure, including upper and lower interconnections, and peripheral transistors with vertical channel structures, allowing for reduced size and integration without additional fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral circuit regions are separated from memory cell array regions in horizontal direction, then signal interference is reduced, but device area increases
Solution Approach 1:
The patent transitions peripheral transistors from planar configuration to vertical channel structures, stacking them above and below the substrate. This vertical stacking in the third dimension reduces the horizontal footprint of the peripheral circuit region while maintaining spatial separation from the memory cell array, thereby reducing device area without compromising signal interference reduction
2Area of stationary object
If vertical channel structures are used for peripheral transistors, then device area is reduced, but fabrication complexity increases
Solution Approach 1:
The patent employs the same vertical channel structure for both memory cell transistors and peripheral transistors. This universal design allows a single fabrication process to manufacture both transistor types simultaneously, eliminating the need for separate fabrication sequences and thereby reducing fabrication complexity despite the vertical architecture
Solution Approach 2:
The patent merges the fabrication processes for memory cell transistors and peripheral transistors into a unified process flow. By combining the formation of vertical channel structures, gate electrodes, and interconnections for both transistor types, the patent reduces overall fabrication complexity while achieving compact peripheral circuit integration
3Productivity
If peripheral transistors are stacked vertically, then integration density is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent segments the peripheral circuit region into multiple vertical layers with interconnection lines positioned at different heights (first level, second level, third level). This segmentation creates thermal pathways through each layer and allows heat to dissipate vertically through the stack, improving heat management while maintaining high integration density
Solution Approach 2:
By transitioning to vertical stacking for both transistors and interconnections, the patent creates additional thermal dissipation pathways in the vertical dimension. The multi-level interconnection structure provides thermal vents and conduction paths that extend heat away from the active transistor regions, addressing heat dissipation challenges associated with high-density vertical integration
Data Source
AI summary
A semiconductor device according to an example embodiment of the present disclosure includes a memory cell array region including memory cells, each of the memory cells including a cell transistor and an information storage structure, and a peripheral circuit region spaced apart from the memory cell array region in a horizontal direction. The peripheral circuit region includes an upper interconnection on a first level, a lower interconnection on a second level that is spaced apart from the first level in a vertical direction that is perpendicular to the horizontal direction, and at least one peripheral transistor between the first level and the second level, where the at least one peripheral transistor includes a channel structure extending in the vertical direction.