Vertical Channel Transistor Pillar Configuration for High Bias Stability
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Solution Overview
Problem
As semiconductor devices integrate more transistors, the reduced gate length and channel length pose challenges in maintaining the integrity of the vertical channel transistor, especially when high bias voltages are applied, leading to potential disturbances in the channel region.
Innovation Solution
The semiconductor device design includes a vertical channel transistor with strategically arranged pillars, bit lines, and contact gates, where the vertical channel region is protected by ensuring a specific distance and configuration to prevent disturbance from high bias voltages, using materials like W, Al, Cu, Mo, Ti, Ta, Ru, and their nitrides or silicides for the bit lines, and insulating layers to maintain channel integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length and channel length are reduced to increase transistor integration, then the number of transistors per unit area increases, but the vertical channel region becomes susceptible to disturbance from high bias voltages applied to bit lines
Solution Approach 1:
The patent transitions from a planar channel configuration to a vertical channel configuration by forming pillars extending in the depth direction. This dimensional change allows the channel to extend vertically through the substrate, increasing the effective channel length without occupying additional planar area, thereby maintaining high integration density while protecting the channel from bit line bias disturbances through proper pillar placement relative to bit lines
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the bit lines and the vertical channel region. This insulating layer acts as a protective barrier that electrically isolates the channel from high bias voltages applied to the bit lines, preventing channel disturbance while allowing the bit lines to function normally for data transmission
2Reliability
If the distance between source and drain regions is increased in a vertical channel transistor, then the effective channel length increases improving transistor performance, but the device occupies more vertical space
Solution Approach 1:
The patent segments the vertical channel structure into distinct components: source/drain regions at the top and bottom, with the channel region in between. The bit lines are positioned to extend between the source and drain regions without interfering with the channel, allowing the channel length to be optimized for performance while the overall vertical height is managed through compact stacking of functional layers
Data Source
AI summary
A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.