Vertical Channel Transistor Pillar Design for Memory Retention
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Solution Overview
Problem
Semiconductor memory devices with vertical channel transistors face issues with current driving capability and data retention due to short channel effects, leading to abnormal device operation and degradation of data retention capability.
Innovation Solution
A semiconductor memory device with a vertical channel transistor design that includes pillars with body and pillar portions, a gate electrode surrounding the pillar portions, a bitline penetrating between the pillar portions, and a wordline contacting the side surface of the gate electrode, along with doped regions and storage node electrodes, to improve current driving capability and prevent body floating phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a vertical channel transistor with floating-body type structure is used, then current driving capability is improved, but holes accumulated in the floating body cause abnormal operation and degradation of data retention capability
Solution Approach 1:
The invention extracts the body portion from the floating-body structure and connects it to the substrate through a dedicated body contact structure. This removes the harmful accumulation of holes in the floating body while preserving the vertical channel's current driving capability. The body is separated into a body portion connected to substrate and pillar portions forming the channel, eliminating the body floating phenomenon.
Solution Approach 2:
The invention introduces an intermediary body contact structure (including body contact plugs and body contact regions) that mediates between the substrate and the pillar portions. This intermediary structure provides a controlled electrical connection that prevents harmful hole accumulation while maintaining proper device operation, resolving the contradiction between current driving capability and data retention.
2Productivity
If design rule is decreased to increase integration, then device density is improved, but short channel effect degrades active switching characteristic
Solution Approach 1:
The invention transitions from planar channel geometry to vertical channel geometry, changing the dimensional orientation of the channel. This vertical configuration allows the channel length to extend in the vertical dimension while maintaining smaller lateral dimensions, enabling high integration density while preserving effective channel length to prevent short channel effects and maintain good switching characteristics.
Data Source
AI summary
In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.