Vertical Channel Transistor Layout for Short-Channel Pixel Circuits
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving transistors with a minute size, short channel length, high on-state current, favorable electrical characteristics, and high reliability, while occupying a small area with low power consumption and high productivity.
Innovation Solution
A semiconductor device is designed with a first and second transistor configuration, utilizing insulating layers and conductive layers with overlapping regions and aligned end portions, allowing for precise control of channel length and reduced area occupation, and incorporating metal oxide semiconductor layers for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the area occupied by transistors is reduced to increase resolution, then the pixel size can be reduced and resolution can be increased, but it becomes difficult to achieve transistors with short channel length, high on-state current, and favorable electrical characteristics
Solution Approach 1:
The patent transitions from a planar transistor structure to a three-dimensional structure where the semiconductor layer extends vertically from the substrate surface. This vertical channel configuration allows the transistor to achieve short channel length and high on-state current while occupying minimal planar area, thereby resolving the contradiction between area reduction and electrical characteristic maintenance.
Solution Approach 2:
The patent employs a stacked configuration where multiple functional layers (semiconductor layer, insulating layers, conductive layers) are nested vertically. The semiconductor layer is positioned between the substrate and the gate electrode, with insulating and conductive layers integrated in a nested manner, enabling compact area occupation while maintaining proper electrical characteristics through controlled layer thicknesses and material properties.
2Area of moving object
If transistors are miniaturized to increase resolution, then pixel size can be reduced, but it becomes challenging to maintain high on-state current and short channel length
Solution Approach 1:
By configuring the semiconductor layer to extend vertically from the substrate surface toward the gate electrode, the patent creates a three-dimensional channel structure. This vertical configuration enables the transistor to achieve both miniaturized planar footprint for high-resolution displays and sufficient channel length for high on-state current, as the effective channel length is determined by the vertical distance rather than horizontal dimensions.
Solution Approach 2:
The patent controls the thickness of the semiconductor layer and the vertical positioning of the gate electrode to optimize the channel length. By adjusting these dimensional parameters, the transistor achieves short channel length for high current drive while maintaining miniaturized pixel size, resolving the contradiction between productivity and area reduction.
Data Source
AI summary
A semiconductor device achieving both low power consumption and high performance is provided. The semiconductor device includes first and second transistors and a first insulating layer. The first transistor includes first to third conductive layers, a first semiconductor layer, and a second insulating layer. The first insulating layer is sandwiched between the first conductive layer and the second conductive layer. The first insulating layer and the second conductive layer include an opening reaching the first conductive layer. In the opening, the first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer. The first semiconductor layer includes a region overlapping with the third conductive layer with the second insulating layer therebetween. The second transistor includes a second semiconductor layer, second and third insulating layers, and a fourth conductive layer. An end portion of the second semiconductor layer is aligned or substantially aligned with an end portion of the third insulating layer. The second semiconductor layer includes a region overlapping with the fourth conductive layer with the second insulating layer and the third insulating layer therebetween.