Vertical Channel Transistor Structure With Plasma-Suppressed Deposition
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Solution Overview
Problem
Existing semiconductor manufacturing technologies face challenges in achieving improved electrical characteristics and reliability, particularly due to difficulties in processing vertical channel transistors and the occurrence of interfacial by-products during channel material deposition.
Innovation Solution
The proposed semiconductor device incorporates a vertical channel transistor structure with a specific manufacturing method that includes forming peripheral circuit structures on a substrate, depositing a semiconductor layer in a trench region, and using a hydrogen plasma surface treatment to suppress deposition on mold patterns, thereby avoiding interfacial by-products and improving channel distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional channel material deposition is performed on mold patterns, then complete coverage is achieved, but interfacial by-products are generated that deteriorate electrical characteristics
Solution Approach 1:
The patent applies preliminary anti-action by performing a surface treatment process on the mold pattern before channel material deposition. This treatment modifies the mold pattern surface to prevent or reduce the formation of interfacial by-products during subsequent deposition, thereby eliminating the harmful effect before it can occur. The surface treatment creates conditions that are unfavorable for by-product generation, resolving the contradiction between achieving complete coverage and avoiding harmful interfacial reactions.
2Manufacturing precision
If etching process is used to form vertical channel structure, then channel shape is defined, but processing complexity and difficulty increase
Solution Approach 1:
The patent extracts and removes the mold pattern after channel material deposition, rather than using it as a permanent etch mask throughout the entire fabrication process. By taking out the mold pattern at an intermediate stage, the process avoids the need for complex multi-step etching operations while still achieving well-defined vertical channel structures. The channel shape is defined during deposition when the mold pattern is present, then the mold is removed, simplifying the overall manufacturing process.
3Productivity
If design rule decreases to improve integration, then transistor density increases, but manufacturing difficulty and reliability challenges increase
Solution Approach 1:
The patent transitions from planar transistor structures to vertical channel transistors, moving the channel extension from two-dimensional lateral scaling to three-dimensional vertical growth. This dimensional change allows continued increase in transistor density and integration as design rules decrease, while the vertical architecture inherently provides better gate control and electrical characteristics that maintain or improve reliability despite scaling challenges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical characteristics and reliability of the semiconductor device by eliminating interfacial by-products and simplifying the etching process, resulting in improved integration, resistance, and current driving ability.
Implementation Method 1
performing a surface treatment process on the mold pattern such that a surface of the mold pattern has hydrophobicity
Implementation Method 2
performing a surface treatment process on the mold pattern such that a surface of the mold pattern has hydrophobicity
Data Source
AI summary
A semiconductor device may include peripheral circuit structures on a substrate, an interlayer insulating layer on the peripheral circuit structure, a bit line extending in a first direction in the interlayer insulating layer, a semiconductor pattern on the bit line, and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other, first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively, and a gate insulating pattern interposed between the first vertical portion and the first word line, and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.