Vertical Channel MOSFET Insulation With Protection Layer
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to increased integration, leading to challenges in achieving superior performance and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with vertically stacked semiconductor patterns, a gate electrode with inner electrodes, and an insulation pattern including a dielectric and protection layer to enhance electrical properties and reliability, while preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density improves, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically stacked 3D channel structures. Multiple semiconductor patterns are stacked vertically to form multi-layer channels, enabling increased device density without further lateral scaling. This dimensional change allows maintaining electrical characteristics while achieving higher integration by utilizing the vertical dimension for additional channel layers.
Solution Approach 2:
The channel region is segmented into multiple discrete semiconductor patterns stacked vertically, with each pattern forming a separate channel layer. These segmented channels are electrically connected through conductive structures, allowing independent control and optimization of each layer's electrical characteristics while achieving high density through vertical stacking.
2Productivity
If vertical stacking of semiconductor patterns is implemented, then device density improves, but leakage current increases
Solution Approach 1:
Insulation patterns are introduced as intermediary structures between the vertically stacked semiconductor patterns and between the semiconductor patterns and the active pattern. These insulation layers act as mediators that electrically isolate adjacent channels, preventing leakage current while maintaining the vertical stacking configuration for high density.
Solution Approach 2:
The harmful leakage current path is extracted or removed by introducing insulation patterns that block current flow between adjacent semiconductor layers. The insulation structures selectively remove or prevent the harmful electrical connection between stacked channels while preserving the desired vertical integration.
3Reliability
If complex gate electrode structures with inner electrodes are used, then electrical properties improve, but device complexity increases
Solution Approach 1:
The gate electrode structure employs nested electrodes where inner electrodes are positioned within or between outer electrode structures. This nested configuration allows multiple gate control functions to be integrated within a compact vertical footprint, improving electrical properties through enhanced gate control while managing complexity through hierarchical structuring.
Data Source
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AI summary
A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.