Vertical Dual Channel Transistor Resistive Memory Cell
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Solution Overview
Problem
Existing resistive memory cell designs are limited by the size of the controller FET or memory element, with planar transistors restricting cell size to at least 8 F^2, and challenges arise in fabricating features like word lines and source lines on non-planar surfaces, leading to issues with misalignment and high resistance.
Innovation Solution
The implementation of buried source lines and vertical channel transistors with a three-dimensional stitching scheme, where a pair of gate electrodes forms a vertical channel on the sidewall of trenches, allowing for shared source lines and reduced cell size to 4 F^2, and the use of a buried word line that connects gates without increasing area, along with self-aligned drain formation and dual channel operation for enhanced current drivability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar FET is used for access transistor, then fabrication is simpler, but cell size is limited to at least 8 F^2
Solution Approach 1:
The patent transitions from planar FET to vertical channel FET, moving the channel from the XY plane to the Z dimension. The vertical channel extends from the source region through the substrate to the drain region, utilizing the third dimension to reduce the footprint of the access transistor while maintaining adequate channel length for control.
Solution Approach 2:
The patent embeds the vertical channel within the substrate structure, nesting the channel region inside the existing substrate volume. The source region is formed in the substrate, and the channel extends vertically through the substrate to the drain, effectively utilizing the substrate's depth to accommodate the transistor structure without increasing surface area.
2Area of stationary object
If vertical channel transistor is used to reduce cell size to 4 F^2, then cell area is reduced, but fabrication complexity increases due to non-planar surface requirements
Solution Approach 1:
The patent performs preliminary actions by first forming the source region in the substrate and creating the vertical channel structure before subsequent processing steps. The channel region is defined early in the fabrication sequence, allowing subsequent gate and contact formation to proceed on a more manageable structure rather than attempting to create vertical features on a non-planarized surface.
Solution Approach 2:
The vertical channel structure serves multiple functions simultaneously: it provides the transistor channel, defines the cell boundary, and creates the necessary vertical separation between source and drain regions. The channel's vertical orientation automatically provides isolation without requiring additional planarization layers or complex alignment steps.
3Area of stationary object
If vertical channel transistor is used, then cell size is reduced to 4 F^2, but source line separation becomes difficult leading to high resistance
Solution Approach 1:
The patent segments the source region into discrete source regions for adjacent memory cells by forming isolation structures between them. The vertical channel and associated source regions are separated by insulating material or doped regions, allowing each cell to have its own dedicated source line path while maintaining compact cell dimensions.
Solution Approach 2:
The patent applies different doping concentrations and types in different regions: the source region has high doping concentration for low resistance contact, the channel region has appropriate doping for transistor operation, and isolation regions have doping profiles designed for electrical separation. This local differentiation of material properties optimizes both resistance and cell separation.
4Ease of operation
If word line is fabricated on non-planar surface, then vertical channel control is achieved, but misalignment with pillars occurs
Solution Approach 1:
The patent establishes the vertical channel structure and source region definitions before forming the word line contacts and gates. By pre-defining the channel location through source region formation and vertical etching or doping, the subsequent word line fabrication can be aligned to these pre-established features rather than attempting to create vertical features on a non-planar surface.
Solution Approach 2:
The vertical channel structure itself provides the alignment reference for word line formation. The channel's vertical orientation and position, defined by the source region and substrate structure, automatically guide the placement of word line contacts and gates without requiring additional alignment marks or planarization steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables miniaturization of resistive memory cells to 4 F^2, reduces cell area, and improves current drivability by using dual channels and buried sources, while addressing fabrication challenges like misalignment and resistance issues.
Implementation Method 1
An extension layer, which is doped to have the opposite type of conductivity than the substrate, is formed on the lower sidewalls of the pillars adjacent to the source line
Implementation Method 2
A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches
Data Source
AI summary
Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.