Vertical Channel Memory Structure With Seam-Isolated Word Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High integration density in memory devices with vertical channel transistors leads to increased interference between neighboring word lines and bit lines, affecting device performance and efficiency.
Innovation Solution
A semiconductor device design featuring bit line structures, semiconductor patterns, insulating interlayer patterns, and word lines with a back gate electrode that applies voltage to opposite channel sides, reducing leakage current and enhancing integration by forming the channel before the back gate electrode, thus improving manufacturing efficiency and reducing threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density is increased in memory devices with vertical channel transistors, then device capacity and compactness are improved, but interference between neighboring word lines and bit lines increases
Solution Approach 1:
A seam is formed in the insulating interlayer pattern between neighboring semiconductor patterns, acting as an intermediary structure that blocks electrical interference between adjacent bit lines while maintaining high integration density. The seam creates an insulating barrier that prevents signal crosstalk without requiring increased spacing between components.
Solution Approach 2:
The insulating interlayer pattern is segmented by forming seams that divide it into isolated regions between neighboring semiconductor patterns. This segmentation creates discrete insulating zones that effectively block interference pathways between adjacent bit lines while preserving the compact vertical channel transistor structure.
2Quantity of substance
If vertical channel transistors are used to increase integration degree, then device compactness is improved, but manufacturing complexity increases
Solution Approach 1:
The channel is formed before the back gate electrode is fabricated, reversing the conventional manufacturing sequence. This preliminary action simplifies the overall manufacturing process by establishing the vertical channel structure first, then adding the back gate electrode as a subsequent layer, reducing the number of complex alignment and patterning steps required.
Solution Approach 2:
The conventional manufacturing sequence is inverted by forming the channel structure before creating the back gate electrode, rather than forming the gate electrode first. This inversion simplifies the manufacturing process for vertical channel transistors by eliminating complex sequential alignment requirements and reducing process steps.
3Reliability
If back gate electrode applies voltage to opposite channel sides, then leakage current is reduced, but device structure becomes more complex
Solution Approach 1:
The back gate electrode serves multiple functions simultaneously: it applies voltage to control leakage current on both sides of the channel, provides mechanical support to the vertical channel structure, and acts as an additional gate for threshold voltage modulation. This multi-functionality reduces the need for separate structures, thereby simplifying the overall device architecture while improving reliability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes bit line structures (360, 350, 340) on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns (137) spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines (305) spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors (700) disposed on and electrically connected to the semiconductor patterns, respectively. A seam (181) extending in the second direction is formed in each of the insulating interlayer patterns (185).