Vertical-Channel Semiconductor Device With Buried Bit Lines

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Solution Overview

Problem

As the degree of integration in semiconductor devices increases, the reduced channel length leads to increased parasitic capacitance and the floating body effect, degrading device characteristics.

Innovation Solution

A vertical-channel semiconductor device is designed with a body-tied structure and buried bit lines, where active pillars are isolated from the substrate by insulation films, and air gaps are formed to reduce parasitic capacitance and prevent the floating body effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the channel length is reduced to increase integration degree, then the device size is reduced, but parasitic capacitance increases and characteristics deteriorate

Engineering Contradiction:
Improvedevice sizeVSAvoiddevice characteristics
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent transitions from planar channel structure to vertical channel structure, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel length to extend in the vertical direction while maintaining a compact horizontal footprint, thereby reducing device area while avoiding excessive parasitic capacitance that would result from horizontal scaling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The active region is segmented into multiple isolated active pillars separated by insulation films. This segmentation creates discrete vertical channels that are electrically isolated from each other, allowing independent control and reducing parasitic interactions between adjacent channels while maintaining high integration density.

Inventive Principle:
Principle #1Segmentation

2Reliability

If active pillars are isolated from substrate by insulation films, then parasitic capacitance is reduced, but floating body effect occurs

Engineering Contradiction:
Improveparasitic capacitance reductionVSAvoidfloating body effect
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A body-tied structure is introduced as an intermediary element that electrically connects the active pillars to the substrate. This mediator provides a path for minority carriers to be collected, preventing charge accumulation in the isolated active pillars and eliminating the floating body effect while maintaining the electrical isolation benefits of the insulation films.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If buried bit lines are disposed below gates, then parasitic capacitance between bit lines is reduced, but device complexity increases

Engineering Contradiction:
Improveparasitic capacitance reductionVSAvoiddevice structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bit line is repositioned from a lateral configuration to a buried vertical configuration below the gates. This dimensional change allows the bit line to be disposed in the vertical direction, increasing the distance between bit lines and reducing parasitic capacitance while integrating the bit line formation into the existing vertical processing steps.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9761710B2Vertical-channel semiconductor device
Publication Date: 2017.09.12 SK HYNIX INC
  • US9761710B2 patent drawing
  • US9761710B2 patent drawing
  • US9761710B2 patent drawing

AI summary

A vertical-channel semiconductor device having a buried bit line is disclosed. The vertical-channel semiconductor device enables an active pillar including a vertical channel region to be separate from a substrate, couples the active pillar to the substrate using a body-tied structure, and prevents a floating body effect from occurring therein. In addition, the vertical-channel semiconductor device includes an air gap between buried bit lines to reduce parasitic capacitance between the bit lines.