Vertical Channel Semiconductor Devices with Silicon Oxynitride Insulation
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Solution Overview
Problem
Current semiconductor devices with vertical channel patterns face challenges in integrating high integration density and maintaining electrical reliability due to limitations in insulating layer composition and processing techniques, particularly with silicon oxynitride films containing nitrogen atoms.
Innovation Solution
The semiconductor device incorporates a silicon oxynitride film with nitrogen atoms between 13% and 21% atomic percent, conformally stacked along with data storage and vertical channel patterns within channel holes, and features a concave portion in the semiconductor substrate to enhance integration density and electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon oxynitride film with high nitrogen content is used as an insulating layer, then electrical reliability is improved, but etch rate control becomes difficult and manufacturing complexity increases
Solution Approach 1:
The patent controls the nitrogen content parameter of the silicon oxynitride film within a specific range (13-21 at%) to optimize both electrical reliability and etch rate controllability. By precisely adjusting this compositional parameter, the film achieves good interface characteristics with the semiconductor substrate while maintaining manageable processing characteristics.
Solution Approach 2:
The patent uses a composite insulating structure comprising multiple layers including silicon oxynitride films with controlled nitrogen content, combined with other insulating materials. This composite approach allows optimization of individual layer properties to achieve both high electrical reliability and processability.
2Quantity of substance
If vertical channel patterns are implemented to increase integration density, then device capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar channel structures to vertical channel patterns, utilizing the vertical dimension to increase integration density. The channel holes extend vertically through multiple insulating layers, allowing higher device capacity without increasing planar footprint.
Solution Approach 2:
The patent performs preliminary formation of insulating patterns and channel holes before depositing data storage and channel patterns. This sequential approach with pre-formed templates ensures precise vertical alignment and reduces manufacturing complexity of the final vertical channel structure.
3Reliability
If conformal stacking of data storage and channel patterns is used, then electrical reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms insulating patterns and channel holes as preliminary structures before conformally stacking data storage and channel patterns. These pre-formed templates guide the subsequent conformal deposition, ensuring proper alignment and reducing the complexity of forming the final stacked structure.
Solution Approach 2:
The patent applies conformal stacking selectively within channel holes rather than uniformly across the entire substrate. This localized approach maintains electrical reliability where needed while reducing overall manufacturing complexity by limiting the conformal process to specific regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves integration density and maintains desired electrical reliability by controlling etch rates and oxidation reactions, ensuring effective contact between patterns and the substrate, thereby enhancing the performance of semiconductor devices.
Implementation Method 1
controlling etch rates and oxidation reactions
Data Source
AI summary
An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.