Vertical Channel Semiconductor Landing Pad Structure
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high element density and small size while maintaining excellent properties and stability, particularly in memory storage applications where increased storage capacity and reduced size are required.
Innovation Solution
A manufacturing method for a semiconductor device that involves forming stacked structures with gate layers and insulating layers, a charge trapping structure, and a channel layer, where part of the charge trapping structure is etched to expose the channel layer, and a landing pad layer is formed to connect with the bit line, reducing contact resistance and avoiding corner edge effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional memory structure is used to increase storage capacity, then element density improves, but device size reduction and stability are compromised
Solution Approach 1:
The patent transitions from planar memory structures to vertical channel structures, utilizing the third dimension (height) to increase element density. The vertical channel extends downward from the surface, allowing more memory elements to be packed in a given footprint while maintaining structural stability through the vertical orientation rather than horizontal expansion.
Solution Approach 2:
The patent implements a nested structure where the vertical channel is surrounded by multiple functional layers including the charge trapping structure, gate layers, and insulating layers. These layers are nested concentrically around the channel, with the charge trapping structure forming an inner cavity that contains trapped charges, creating a compact nested arrangement that maximizes density while maintaining stability.
2Volume of moving object
If the charge trapping structure is made thinner to reduce device size, then storage capacity increases, but connection stability with bit line deteriorates
Solution Approach 1:
The patent compensates for the reduced thickness of the charge trapping structure by extending the channel and landing pad in the vertical dimension. The landing pad extends downward below the charge trapping structure, providing a larger vertical footprint for connection to the bit line, thus maintaining connection stability despite the reduced horizontal thickness of the charge trapping layer.
Solution Approach 2:
The patent changes the geometric parameters of the landing pad, making it both thick and wide to provide stable mechanical and electrical connection. The landing pad's increased thickness compensates for the thinner charge trapping structure, ensuring adequate connection stability while the overall device footprint is reduced through the vertical channel architecture.
3Volume of moving object
If a thin landing pad is formed to reduce device size, then storage capacity increases, but contact resistance increases and corner edge effects occur
Solution Approach 1:
The patent resolves the corner edge effect by transitioning from a planar landing pad to a vertical extension structure. The landing pad extends downward in the vertical dimension rather than expanding horizontally, which eliminates the corner edge regions where programming/erasing issues occur in conventional planar structures. This vertical extension provides adequate contact area without creating problematic corner edges.
Solution Approach 2:
The patent extracts the problematic corner edge regions by using a vertical extension geometry for the landing pad. By extending downward rather than expanding horizontally with corners, the design eliminates the corner edge areas that cause programming/erasing issues, while still providing sufficient contact area for low contact resistance through the vertical footprint.
Data Source
AI summary
A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.