Vertical Channel Semiconductor Device Reducing Saturation Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power transistors, such as IGBTs, face challenges in minimizing collector-emitter saturation voltage (VCEsat), which affects leakage when the device is on, and current technologies have not effectively reduced this voltage without increasing switch-off energy or resorting to miniaturization.
Innovation Solution
A vertical channel semiconductor device is designed with a specific trench structure and emitter region configuration, including staggered trenches and insulating layers, which increases carrier concentration in certain regions, reducing VCEsat without the need for advanced miniaturization technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional trench structures are used in power transistors, then manufacturing is simpler, but VCEsat cannot be effectively reduced
Solution Approach 1:
The device is divided into multiple semiconductor regions (first, second, third, fourth regions) separated by alternating conductive and insulating trench portions. This segmentation creates distinct functional zones that control carrier concentration distribution, enabling reduced VCEsat through optimized current flow paths while maintaining manageable structural complexity.
Solution Approach 2:
Different trench portions are assigned different electrical properties (conductive vs. insulating) to create localized regions with specific carrier concentration characteristics. The first and second conductive trench portions create high carrier concentration zones, while insulating portions maintain lower concentrations, optimizing VCEsat locally in different device regions.
2Loss of energy
If miniaturization technologies are used to reduce VCEsat, then VCEsat decreases, but manufacturing complexity and costs increase
Solution Approach 1:
The invention reduces VCEsat by changing the electrical parameters (carrier concentration) through the strategic placement of conductive and insulating materials in trench portions, rather than relying on miniaturization. This approach achieves voltage reduction through material property optimization and structural configuration, maintaining compatibility with existing manufacturing capabilities.
3Loss of energy
If carrier concentration is increased to reduce VCEsat, then VCEsat decreases, but switch-off energy may increase
Solution Approach 1:
The device creates localized high carrier concentration regions only where needed (in the first and second semiconductor regions bounded by conductive trenches) rather than uniformly increasing concentration throughout the entire device. This localized approach reduces VCEsat in critical areas while minimizing the overall energy stored that would need to be dissipated during switch-off.
Solution Approach 2:
By segmenting the device into regions with different carrier concentrations separated by insulating trenches, the invention confines high carrier concentration to specific areas. This segmentation prevents excessive energy accumulation in non-critical regions, thereby reducing the total switch-off energy requirement while maintaining low VCEsat in the active regions.
Data Source
AI summary
A vertical channel semiconductor device including: a semiconductor body including a substrate having a first conductivity type and a front layer having a second conductivity type; a first portion of trench and a second portion of trench; and, within the first and second portions of trench, a corresponding conductive region and a corresponding insulating layer. The first and second portions of trench delimit laterally a first semiconductor region and a second semiconductor region, the first semiconductor region having a maximum width greater than the maximum width of the second semiconductor region. The device further includes an emitter region having the first conductivity type, which extends in the front layer and includes: a full portion, which extends in the second semiconductor region; and an annular portion, which extends in the first semiconductor region. The annular portion laterally surrounds a top region having the second conductivity type.