Vertical-Channel Silicon FET Fabrication Process
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Solution Overview
Problem
Conventional silicon field-effect transistors with non-coplanar source/drain diffusions do not effectively couple between coplanar but horizontally-separated source/drain regions, limiting their application in high-power switching and image sensor circuits where small cell size and minimized pixel area are required.
Innovation Solution
A new fabrication process for vertical-channel insulated-gate transistors involves etching a wide trench, forming a dielectric, depositing a flowable material, creating an inner trench, epitaxially growing a semiconductor strip, growing a gate oxide, and forming a gate conductor, which allows for a vertical gate structure that enhances coupling between coplanar source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional non-coplanar source/drain diffusions are used, then high-power switching capability is achieved, but coupling between coplanar source/drain regions is ineffective
Solution Approach 1:
The invention transitions from planar 2D channel structure to a vertical 3D channel structure by etching trenches into the substrate and growing semiconductor strips vertically. This dimensional change allows the gate to wrap around the semiconductor strip, creating effective coupling between coplanar source and drain regions while maintaining high-power switching capability through the vertical channel configuration.
2Reliability
If vertical gate structure is implemented, then coupling between coplanar source/drain regions is enhanced, but device complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: trench etching, dielectric deposition, semiconductor strip epitaxial growth, gate oxide formation, and gate conductor deposition. Each stage is independently optimized and controlled, allowing the complex vertical gate structure to be manufactured through systematic breakdown of the fabrication process into manageable steps.
Solution Approach 2:
The structure employs nested configurations where the gate conductor wraps around the semiconductor strip, which is embedded within the dielectric material, which in turn is contained within the trench. This nested arrangement achieves effective coupling between coplanar source/drain regions while organizing the complex structure in a hierarchical manner that simplifies fabrication.
3Area of stationary object
If vertical-channel transistor structure is used, then pixel area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The invention applies local quality by creating vertically-oriented trenches with specific depth and width characteristics in localized regions of the substrate. The epitaxial growth is confined to these predefined trench regions, allowing precise control over semiconductor strip formation. This localized approach reduces overall pixel area while maintaining high manufacturing precision through region-specific process optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process results in transistors with an effective gate width greater than conventional planar transistors, enabling their use as source-follower and reset transistors in image sensor circuits with reduced pixel area and improved performance.
Implementation Method 1
forming a dielectric in and around the wide trench
Implementation Method 2
depositing a flowable material into the wide trench
Implementation Method 3
epitaxially growing a semiconductor strip seeded by the well or substrate within the inner, narrow, trench
Implementation Method 4
growing a gate oxide on the semiconductor strip
Data Source
AI summary
A method of fabricating transistors with a vertical gate in trenches includes lithographing to form wide trenches; forming dielectric in the trenches and filling the trenches with flowable material; and lithography to form narrow trenches within the wide trenches thereby exposing well or substrate before epitaxially growing semiconductor strips atop substrate exposed by the narrow trenches; removing the flowable material; growing gate oxide on the semiconductor strip; forming gate conductor over the gate oxide and into gaps between the epitaxially-grown semiconductor strips and the dielectric; masking and etching the gate conductor; and implanting source and drain regions. The transistors formed have semiconductor strips extending from a source region to a drain region, the semiconductor strips within trenches, the trench walls insulated with a dielectric, a gate oxide formed on both vertical walls of the semiconductor strip; and gate material between the dielectric and gate oxide.