Vertical Channel 3D NAND Memory With Split Channel Architecture
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Solution Overview
Problem
Current three-dimensional memory technologies face limitations in data storage density due to the large cross-section of column and dielectric charge trapping structures, which restricts the density of data storage even with high-density flash technologies, and require fine control over threshold voltages for multiple-bit-per-cell programming.
Innovation Solution
A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, allowing for multiple bit per site operation, with control circuitry applying different bias voltages to even and odd conductive strips to store more than one bit of data in each memory cell, and utilizing a multilayer array of interface regions between active pillars and conductive strips for enhanced data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a column and dielectric charge trapping structure is used to limit disturbance, then read and program disturb characteristics are improved, but the cross-section area increases and data storage density is limited
Solution Approach 1:
The vertical channel is divided into two separate channels, each with its own charge trapping structure and control gates. This segmentation allows independent operation of the two channels, enabling double the memory sites per vertical column while maintaining compact dimensions. Each channel can be independently controlled and programmed, achieving both high density and reliable disturbance characteristics.
Solution Approach 2:
The patent transitions from a single vertical channel architecture to a dual vertical channel architecture, effectively utilizing the vertical dimension more efficiently. By stacking multiple channels vertically and providing independent control through separate gate structures, the design achieves higher storage density without increasing the lateral cross-section area.
2Quantity of substance
If multiple-bit-per-cell programming is implemented, then data storage density is improved, but fine control over threshold voltages is required making read and program disturb characteristics more critical
Solution Approach 1:
By segmenting the memory into two independent channels with separate charge trapping structures, each channel can store multiple bits independently. This segmentation simplifies the voltage control requirement compared to attempting to store multiple bits in a single channel, as each channel's threshold voltage can be controlled separately through its own control gates, reducing the overall manufacturing precision burden.
Solution Approach 2:
The patent employs independent control gates for each channel that can apply different voltages to adjust threshold voltages precisely. By changing the voltage parameters applied to each control gate independently, the system achieves fine control over threshold voltages for multiple-bit storage without requiring extremely precise manufacturing tolerances.
3Ease of operation
If vertical NAND gate structure with silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology is used, then vertical channel memory is achieved, but the column cross-section remains relatively large limiting three-dimensional memory density
Solution Approach 1:
The vertical channel is segmented into two independent channels, each with its own SONOS charge trapping structure. This segmentation doubles the memory capacity per vertical column without increasing the overall column cross-section, as both channels share the same vertical space. The segmented structure maintains the ease of vertical channel operation while achieving higher three-dimensional memory density.
Solution Approach 2:
Two complete vertical NAND gate structures with SONOS charge trapping are merged into a single integrated unit, sharing common substrates and interlayer dielectrics. This merging achieves high memory density by packing two functional channels into one column structure while maintaining the operational characteristics of individual vertical channels.
Data Source
AI summary
A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip.