Vertical Channel Transistors for Compact SRAM Cell Design
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high integration and efficient manufacturing of static random access memory (SRAM) cells due to the larger planar area required by SRAM cells compared to dynamic random access memory (DRAM) cells, which affects operational speed and power consumption.
Innovation Solution
The development of highly integrated SRAM cells with a specific configuration including access gates, shared gates, vertical channel portions, and node electrodes, along with a method of manufacturing that involves forming sacrificial layers, capping insulating layers, and epitaxial processes to create vertical channel transistors, reducing the occupied area and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional planar SRAM cell configuration is used, then operational speed and power consumption are maintained, but planar area occupied is larger
Solution Approach 1:
The patent transitions from planar 2D transistor configuration to vertical 3D configuration by forming vertical channel portions that extend through the substrate thickness. The vertical channel portions penetrate through the substrate with gate electrodes wrapped around them, creating a three-dimensional structure that reduces the lateral footprint of each SRAM cell while maintaining functional performance
Solution Approach 2:
The gate electrodes are wrapped around the vertical channel portions in a nested configuration. The first and second gate electrodes are positioned at different heights along the vertical channel, with each gate electrode surrounding the channel portion it controls. This nested arrangement allows multiple gating functions within a compact vertical space, reducing the overall planar area requirement
2Productivity
If vertical channel transistors are implemented, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct sequential stages: forming sacrificial layers at specific positions, depositing gate electrode materials, performing epitaxial growth to create vertical channel portions, removing sacrificial layers, and forming gate dielectric layers. Each stage is independently controllable and optimized, making the complex vertical structure manufacturable through standardized semiconductor processes
Solution Approach 2:
Sacrificial layers are introduced as temporary intermediary structures during manufacturing. These sacrificial layers are positioned where vertical channels should eventually form, allowing gate electrodes to be deposited and epitaxial growth to occur around them. The sacrificial layers are subsequently removed, leaving clean vertical channel structures. This intermediary approach simplifies the overall manufacturing sequence by enabling self-aligned formation of complex vertical features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration and manufacturing method enable a more compact and efficient SRAM cell design, improving operational speed and reducing power consumption while maintaining high integration, thus addressing the area and efficiency challenges of traditional SRAM cell manufacturing.
Implementation Method 1
performing an epitaxial process using the substrate exposed by the channel holes as a seed, thereby growing vertical channel portions in the channel holes
Data Source
AI summary
A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.