Vertical Channel Tapering for Enhanced GIDL Current in 3D NAND
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high speed erase operations due to insufficient gate-induced drain leakage (GIDL) current, which is crucial for efficient data erasure in vertical NAND strings.
Innovation Solution
The design involves a three-dimensional memory device structure with an alternating stack of insulating and conductive layers, including word lines between source and drain select gate electrodes, a memory opening extending through the stack, and a vertical semiconductor channel with a p-n junction, where the end portion has a thicker thickness than the middle portion to enhance GIDL current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional vertical NAND string structure with uniform channel thickness is used, then the device structure is simple and easy to manufacture, but the gate-induced drain leakage (GIDL) current is insufficient for high speed erase operations
Solution Approach 1:
The patent applies local quality by creating a vertical semiconductor channel with non-uniform thickness, where the end portion has a first thickness and the middle portion has a second thickness that is less than the first thickness. This localized variation in channel thickness specifically enhances the GIDL current generation at the drain region while maintaining the overall vertical channel structure, thereby improving erase operation speed without completely redesigning the entire device architecture.
Solution Approach 2:
The patent introduces dimensional variation by transitioning from a uniform thickness channel to a tapered or non-uniform thickness channel structure. This dimensional change in the vertical channel allows for enhanced electric field distribution and improved GIDL current generation, enabling faster erase operations while building upon the existing vertical NAND string architecture.
2Productivity
If the vertical semiconductor channel has uniform thickness throughout, then the manufacturing process is simpler, but the electrical field strength and electron-hole pair generation are insufficient for efficient data erasure
Solution Approach 1:
The patent implements local quality by varying the channel thickness specifically at different portions of the vertical semiconductor channel. The end portion maintains a first thickness while the middle portion has a reduced second thickness, creating localized regions with different electrical characteristics that enhance electron-hole pair generation and electric field strength where needed, without complicating the entire manufacturing process.
Solution Approach 2:
The patent applies parameter changes by modifying the physical dimension (thickness) of the vertical semiconductor channel along its length. This parameter variation in channel thickness directly affects the electric field distribution and carrier generation characteristics, enabling improved data erasure efficiency through enhanced GIDL current while using standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases the GIDL current, enabling faster erase operations by enhancing electron-hole pair generation and electrical field strength, thus improving the speed and efficiency of data erasure in three-dimensional NAND memory devices.
Implementation Method 1
structures for enhancing gate-induced drain leakage current for high speed erase operations
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.