Thin Film Transistor Fabrication via Vertical Channel Extension
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Solution Overview
Problem
Conventional pixel structures have an unfavorable aperture ratio due to the increased area occupied by active devices, which affects the conductivity performance and overall efficiency of display devices.
Innovation Solution
A fabricating method for a thin film transistor (TFT) that includes forming a substrate with a source, insulation pattern layers, a gate pattern layer, a channel layer, and a passivation layer, where the thickness and profiles of these layers are carefully controlled to optimize the channel layer length without increasing the device's area, thereby improving conductivity and aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length and width of the channel layer are increased to improve conductivity performance, then the conductivity performance is improved, but the area occupied by the active device increases and the aperture ratio decreases
Solution Approach 1:
The patent transitions from a conventional planar channel structure to a three-dimensional vertical channel structure by forming the channel layer to extend upward from the substrate through the gate structure. This vertical extension allows the channel length to be increased in the vertical dimension rather than horizontally, thereby improving conductivity without increasing the lateral area occupied by the device, thus maintaining a high aperture ratio.
2Area of stationary object
If the area occupied by the active device is reduced to improve aperture ratio, then the aperture ratio is improved, but the conductivity performance deteriorates
Solution Approach 1:
The invention utilizes the vertical dimension to accommodate the channel layer, allowing it to extend upward through the gate structure. This enables sufficient channel length for good conductivity performance while keeping the lateral footprint minimal, thereby achieving high aperture ratio without sacrificing conductivity.
Solution Approach 2:
The channel layer is nested within the vertical structure formed by the gate and insulation layers. The channel extends upward from the substrate, passing through the gate region, and continues above the gate structure. This nested configuration allows the channel to achieve sufficient length for good conductivity while being contained within a compact lateral footprint, thus maintaining high aperture ratio.
3Ease of manufacture
If a conventional bottom gate structure is used, then the manufacturing process is simple, but the channel layer length is limited and conductivity performance is insufficient
Solution Approach 1:
The gate structure is segmented into multiple parts: a first gate portion formed on the substrate, and a second gate portion formed above the first gate portion. This segmentation allows the channel layer to extend through both gate portions, effectively increasing the channel length and improving conductivity performance while maintaining a systematic manufacturing approach.
Solution Approach 2:
The patent extends the gate structure vertically by forming a second gate portion above the first gate portion. This vertical segmentation allows the channel layer to achieve greater length by passing through multiple gate levels, thereby improving conductivity performance while maintaining ease of manufacture through systematic layer formation.
Data Source
AI summary
A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer.