Vertical Channel TFT for High-Resolution Flexible Displays
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Solution Overview
Problem
As display devices strive for higher resolution, the size of individual pixel areas in thin film transistor array substrates decreases, posing challenges in maintaining characteristic conditions and efficiently utilizing limited pixel space while ensuring uniformity and flexibility in deformation such as bending.
Innovation Solution
The thin film transistor array substrate design includes a base substrate with integrated transistors and a storage capacitor, utilizing spacers of varying heights to optimize transistor channel lengths and reduce area occupancy, along with a pixel electrode that overlaps with transistors and capacitors, and a fabricating method that forms these components in layers to enhance efficiency and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pixel area is reduced to achieve higher resolution, then the resolution is improved, but the transistor channel length becomes insufficient and manufacturing becomes more difficult
Solution Approach 1:
The transistor channel is configured to extend in the vertical direction (thickness direction of the substrate) rather than only in the horizontal plane. This three-dimensional channel structure allows sufficient channel length to be achieved within the reduced pixel area, resolving the contradiction between high resolution and adequate transistor channel dimensions.
Solution Approach 2:
The pixel circuit components (transistors and capacitors) are nested within the pixel area in a compact three-dimensional arrangement. The vertical channel structure enables components to be stacked or arranged in multiple layers, maximizing space utilization and maintaining sufficient channel length despite the reduced horizontal pixel dimensions.
2Measurement precision
If the pixel area is reduced to achieve higher resolution, then the resolution is improved, but the pixel area occupancy increases and space utilization becomes inefficient
Solution Approach 1:
By transitioning from a two-dimensional to three-dimensional transistor channel structure, the patent reduces the horizontal footprint of each transistor. This allows more efficient packing of pixel circuit components within the reduced pixel area, improving space utilization while maintaining adequate channel length for transistor operation.
Solution Approach 2:
The pixel circuit is segmented into multiple functional components (first transistor, second transistor, storage capacitor) that are arranged in a compact three-dimensional configuration. This segmentation allows optimized spatial distribution of components, reducing overall pixel area occupancy while ensuring each component has sufficient dimensions for proper function.
3Productivity
If the transistor channel length is reduced to fit more pixels, then the pixel density is improved, but the transistor characteristic uniformity during deformation deteriorates
Solution Approach 1:
The vertical channel configuration provides mechanical stability and consistent electrical characteristics during substrate deformation. The channel extending in the thickness direction maintains uniform stress distribution and electrical properties even when the substrate is bent or flexed, ensuring reliable transistor operation across the entire display panel.
Solution Approach 2:
The transistor structure is designed with specific local characteristics including the vertical channel orientation and gate electrode positioning that optimize performance for flexible applications. This localized structural quality ensures uniform transistor characteristics are maintained specifically in regions subject to deformation, while other areas can be optimized for different functions.
Data Source
AI summary
A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.