Vertical Channel TFT Structure for Higher Electron Mobility
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Solution Overview
Problem
Conventional semiconductor devices, particularly TFTs in display panels, face challenges such as low electron mobility, poor stability, and high production costs, which hinder their ability to meet the requirements of larger-size and high-refresh-rate displays.
Innovation Solution
The semiconductor device incorporates a vertical channel TFT structure, where the semiconductor layer is disposed on the source and the drain is disposed on the semiconductor layer, with the gate positioned to form a vertical channel, enhancing carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional self-aligned top-gate TFT structure is used, then the manufacturing process is simplified, but the electron mobility is low and device performance is poor
Solution Approach 1:
The patent transitions from a conventional planar TFT structure to a vertical channel TFT structure by stacking the source, semiconductor layer, and drain in vertical layers. The gate electrode wraps around the semiconductor layer from both sides, creating a vertical current flow path instead of horizontal flow. This dimensional change increases the effective channel area and improves electron mobility while maintaining manufacturing feasibility through modified deposition and etching processes.
2Reliability
If the TFT structure is optimized for higher performance, then electron mobility improves, but the manufacturing process becomes more complicated and production costs increase
Solution Approach 1:
The patent segments the gate electrode into multiple parts: a first gate electrode on one side of the semiconductor layer, a second gate electrode on the other side, and potentially a third gate electrode at the bottom. This segmentation allows each gate portion to be independently formed and controlled, enabling optimized electric field distribution for high electron mobility while using standard deposition and patterning processes that don't significantly complicate manufacturing.
3Productivity
If conventional TFT structures are used in large-size panels, then production costs are high, but the device performance is insufficient for high refresh rate displays
Solution Approach 1:
The patent changes key structural parameters of the TFT: the channel length is reduced by forming shorter vertical channels, the channel width is increased through extended semiconductor layer coverage, and the gate electrode dimensions are optimized to wrap around the semiconductor layer. These parameter changes improve electron mobility and device performance for high refresh rate displays while using conventional materials and processes that don't significantly increase production costs for large-size panels.
Data Source
AI summary
The present disclosure provides a semiconductor device and a method for preparing same. The semiconductor device includes a substrate, a source, a semiconductor layer, a drain, an insulating layer, and a gate. A main body portion of the source and a main body portion of the drain are disposed on different faces. The semiconductor layer is disposed between the source and the drain. The gate is disposed on a side of the semiconductor layer. Therefore, a vertical channel thin film transistor (TFT) is formed. In this way, the mobility of carriers in the TFT and the performance of the semiconductor device are effectively improved.