Vertical Channel Thin Film Transistor with Spacer-Defined Length
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Solution Overview
Problem
Current display technologies face challenges in achieving high-resolution images with compact thin film transistors that integrate both vertical channels and capacitors effectively, limiting their size reduction and integration density.
Innovation Solution
A thin film transistor design featuring a substrate with a gate electrode having a center and peripheral part, a semiconductor layer connecting perpendicular electrodes, and a spacer that adjusts the channel length, along with an overlap capacitor configuration, allowing for reduced size and high-density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical channel structure is used to reduce transistor size, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The spacer acts as an intermediary element that defines the channel length between the first and second electrodes. By controlling the spacer thickness rather than directly patterning the electrode ends, the channel length is precisely controlled through a single deposition process, reducing manufacturing complexity and improving precision in vertical channel structures
Solution Approach 2:
The channel length is controlled by changing the thickness parameter of the spacer layer through deposition process control. This allows precise adjustment of channel length (e.g., 50nm to 200nm) by controlling the spacer deposition thickness, providing a reliable method to achieve high integration density with controlled manufacturing precision
2Reliability
If electrode overlap area is increased to form effective capacitor, then capacitance is improved, but transistor area increases
Solution Approach 1:
The capacitor is formed in the vertical dimension through the overlap of the first electrode with the gate electrode and the second electrode with the gate electrode in the thickness direction. This vertical overlap configuration provides effective capacitance without requiring additional horizontal area, enabling high integration density while maintaining sufficient capacitance for display operation
Solution Approach 2:
The capacitor structure is nested within the transistor structure by utilizing the gate electrode as one of the capacitor electrodes. The first and second electrodes are positioned to overlap with the gate electrode in the vertical direction, creating a compact nested configuration where the capacitor function is integrated into the transistor structure without occupying separate area
Data Source
AI summary
A thin film transistor includes a substrate and a gate electrode disposed over the substrate. The gate electrode includes a center part and a peripheral part configured to at least partially surround the center part. The thin film transistor further includes a gate insulating layer disposed below the gate electrode and a first electrode insulated from the gate electrode by the gate insulating layer. The first electrode has at least a portion thereof overlapping the center part. The thin film transistor additionally includes a spacer disposed below the first electrode and a second electrode insulated from the first electrode by the spacer. The second electrode has at least a portion thereof overlapping the peripheral part. The thin film transistor further includes a semiconductor layer connected to the first and second electrodes, and insulated from the gate electrode by the gate insulating layer.