Vertical Channel Transistor Array With Embedded Word Lines
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size of semiconductor devices while maintaining electrical performance, particularly due to the short channel effect in transistors, which affects the ON current and overall device efficiency.
Innovation Solution
A vertical channel transistor array is developed with embedded bit lines and word lines formed in trenches, where the word lines are selectively connected to one side of semiconductor pillars, and an isolation structure is used between adjacent word lines to prevent interference and enhance channel area, along with a manufacturing method that includes tilted ion implantation and a hard mask to reduce feature size and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length of transistors is decreased to reduce device dimension, then the operation speed is accelerated, but the short channel effect occurs and ON current decreases
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, changing the channel direction from horizontal to vertical. This dimensional change allows the channel to extend through the thickness of the semiconductor layer, enabling shorter channel lengths while maintaining better control over the channel region and reducing the short channel effect.
Solution Approach 2:
The patent embeds the channel region within a three-dimensional structure where the channel is surrounded by gate structures on multiple sides. This nested configuration provides superior electrostatic control over the channel, allowing shorter channel lengths without significant degradation of ON current due to the short channel effect.
2Productivity
If the device dimension is reduced to increase integration, then the transistor density increases, but the manufacturing complexity and process control difficulty increase
Solution Approach 1:
The patent divides the semiconductor structure into discrete vertical pillars or nanowires separated by isolation regions. This segmentation approach enables independent formation and control of each transistor channel, simplifying the manufacturing process while achieving high density through closely spaced vertical structures.
Solution Approach 2:
The vertical channel structure self-aligns with the substrate and surrounding gate structures, reducing the need for complex alignment steps. The inherent geometry of vertical channels provides natural registration with overlying and underlying layers, simplifying the manufacturing process compared to planar structures requiring multiple precise alignment operations.
3Quantity of substance
If multiple word lines are formed to increase memory capacity, then the storage density increases, but the risk of short circuits and abnormal connections between adjacent word lines increases
Solution Approach 1:
The patent introduces isolation structures (such as dielectric materials or air gaps) as intermediary elements between adjacent vertical channels and word lines. These isolation structures physically separate conductive elements, preventing direct electrical contact and short circuits while allowing closely spaced routing of multiple word lines to increase memory capacity.
4Area of stationary object
If the vertical channel transistor structure is implemented to reduce device footprint, then the area per transistor decreases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps that define the vertical channel locations before subsequent processing. By establishing the channel positions early in the fabrication sequence using robust lithography and etching steps, the design rules can be optimized for these critical dimensions, achieving the required manufacturing precision for reduced device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device dimension, increases channel area, and effectively prevents short channel effects, thereby improving device performance and preventing short circuits and abnormal connections.
Implementation Method 1
the manufacturing method that includes tilted ion implantation
Data Source
AI summary
A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall.