Vertical Channel Transistor Sidewall Doping via Sacrificial Pattern Windows
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Solution Overview
Problem
Current semiconductor devices with vertical channel transistors face challenges in forming efficient doped regions and wiring connections within trenches, which can lead to electrical isolation and reduced conductivity.
Innovation Solution
A method involving patterning a substrate to form trenches, depositing sacrificial patterns, forming spacers, recessing the sacrificial patterns to create windows, doping the sidewalls, and forming wiring connections to the doped regions, ensuring the doped regions have a different conductivity type from the substrate and are spaced apart from the trench bottom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring is formed to connect to doped regions, then electrical connectivity is enhanced, but device complexity increases
Solution Approach 1:
The patent combines the formation of the doped region and the wiring structure into an integrated fabrication process. The doped region is formed on the trench sidewall during the same fabrication sequence that creates the active region and gate structure, and the wiring is subsequently formed to connect to this doped region, merging multiple functions into a unified structure rather than adding separate complex components.
2Reliability
If the doped region is formed close to the trench bottom, then electrical connection to substrate is improved, but the doped region may interfere with trench filling
Solution Approach 1:
The patent applies local quality by forming the doped region specifically on the sidewall of the trench rather than uniformly across the entire trench bottom or sidewall. This localized doping creates the necessary electrical connection to the substrate while leaving the trench bottom and other areas available for subsequent filling operations with semiconductor material or insulating material, thus avoiding interference with trench filling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of semiconductor devices with vertical channel transistors that have improved electrical connectivity and reduced risk of electrical isolation, enhancing the device's conductivity and performance.
Implementation Method 1
The spacer may include a material having etch selectivity with respect to at least one of the insulating layer and the sacrificial layer
Implementation Method 2
doping the semiconductor pattern with impurities, and diffusing the impurities into the active region
Implementation Method 3
anisotropically etching the semiconductor layer to form a semiconductor pattern locally remaining between the spacer and the sacrificial pattern
Data Source
AI summary
A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.