Vertical Channel Transistor Fabrication for High Integration
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Solution Overview
Problem
Current methods for fabricating transistors with horizontal channels face challenges in improving integration, resistance, and current driving capability, particularly in achieving reproducible channel lengths and reducing buried bit line resistance.
Innovation Solution
A method for fabricating vertical channel transistors involves forming active patterns, vertical channels, buried bit lines, and word lines on a substrate, utilizing insulating layers and metal deposition to enhance electrical characteristics and current driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If horizontal channel transistors are used, then fabrication is simpler, but integration and current driving capability are limited
Solution Approach 1:
The patent transitions from horizontal channel transistors to vertical channel transistors, changing the spatial dimension of the channel from in-plane to out-of-plane. This dimensional change enables higher integration density while maintaining fabrication feasibility through adapted process steps including trench formation, insulation layer deposition, and metal line formation at different orientations.
2Productivity
If channel length is reduced for higher integration, then integration improves, but channel length reproducibility becomes difficult to control
Solution Approach 1:
The patent forms insulation layers and defines channel regions through preliminary trench formation and material deposition steps before final transistor fabrication. This preliminary structuring establishes precise geometric boundaries that ensure reproducible channel lengths even as dimensions are reduced for higher integration, allowing controlled scaling while maintaining manufacturing precision.
3Speed
If buried bit line resistance is reduced for faster operation, then operational speed improves, but fabrication complexity increases
Solution Approach 1:
The patent forms buried bit lines extending in the first horizontal direction beneath the vertical channel structure, utilizing the vertical dimension to route bit lines through insulated regions. This three-dimensional routing enables lower resistance paths for current flow while maintaining fabrication feasibility through sequential deposition and patterning steps, achieving faster operational speed without excessive complexity increase.
Data Source
AI summary
A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate; forming a buried bit line extending in the first horizontal direction on the substrate; and forming a word line extending in the second horizontal direction along at least one side surface of the vertical channel.