Vertical Channel Transistor Fin Structure for Short Channel Effect Control
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Solution Overview
Problem
Current semiconductor manufacturing technologies face limitations in producing high-resolution planar transistors due to electrostatic discharge, leakage, and decreased electron mobility, leading to short channel effects and drain-induced barrier lowering, which hinder the scalability and efficiency of conventional transistors, while advanced vertical channel transistors like fin FETs require expensive processes and result in poor uniformity and stability.
Innovation Solution
A vertical channel transistor structure with a fin-shaped channel and a manufacturing method that involves forming a fin-shaped structure on a substrate, depositing a cap layer and charge trapping layer, and positioning a gate over the vertical surfaces, allowing for increased driving current without short channel effects, and using a SiN layer as a hard mask to reduce channel width and improve etching uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography process is used to manufacture planar transistors, then manufacturing cost is reduced, but resolution and transistor quality deteriorate due to electrostatic discharge, leakage, and short channel effects
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors by changing the channel orientation from horizontal to vertical. The channel extends vertically through the fin structure, allowing the gate to control current flow from top to bottom rather than side to side. This dimensional change enables higher packing density and improved scalability while maintaining compatibility with existing photolithography processes.
Solution Approach 2:
The patent divides the channel into multiple vertical segments along the fin structure, with the gate wrapping around to form double-gate or tri-gate configurations. This segmentation allows each gate to control a specific portion of the channel, improving electrostatic control and reducing short channel effects while maintaining manufacturability.
2Manufacturing precision
If expensive photolithography or E-beam processes are used to manufacture fin FET, then transistor resolution is improved, but productivity deteriorates due to low throughput
Solution Approach 1:
By orienting the channel vertically and using the fin structure, the patent achieves high-resolution transistor features using standard photolithography processes. The vertical orientation allows better control of critical dimensions and reduces the need for expensive advanced lithography techniques, thereby maintaining high throughput.
3Length of moving object
If oxidation is applied to etched channel to reduce channel width, then element size is reduced, but manufacturing precision deteriorates due to poor uniformity and unstable quality
Solution Approach 1:
The patent performs etching to define the channel width before oxidation is applied. By establishing the critical dimensions through controlled etching with proper masking, the subsequent oxidation step can proceed uniformly without causing variability. This preliminary definition of geometry ensures consistent channel dimensions and high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables increased memory density and improved transistor efficiency by enhancing driving current and preventing short channel effects, allowing for large-scale production of high-resolution transistors with improved uniformity and stability at a lower cost.
Implementation Method 1
The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure
Implementation Method 2
The gate straddles on the charge trapping layer and is positioned on the two vertical surfaces of the fin-shaped structure
Implementation Method 3
The channel of the transistor structure is formed on a semiconductor body which protrudes from the substrate in a fin-shaped structure
Data Source
AI summary
A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.