Vertical Channel Transistor Floating Body Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices with vertical channel transistors face challenges in reducing the floating body effect and dynamic reference properties, leading to instability and performance deterioration due to the floating state of the channel region.
Innovation Solution
The semiconductor memory device incorporates a semiconductor substrate with a semiconductor pillar having distinct regions, where the second region is electrically separated and used as the channel region of one field effect transistor, and the third region is used as the drain electrode of another, with gate patterns and insulating layers strategically positioned to control electrical characteristics and suppress the floating body effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the channel region is left in a floating state to reduce device complexity, then the manufacturing process is simplified, but the device exhibits floating body effect and dynamic reference property deterioration leading to instability
Solution Approach 1:
The semiconductor pillar is divided into multiple doped regions (first region, second region, third region) with different conductivity types. The channel region is segmented and electrically connected to the substrate through the third region, eliminating the floating body effect while maintaining a compact vertical structure.
Solution Approach 2:
The third region acts as an intermediary conductive path between the channel region and the substrate. This intermediary structure provides electrical connection to suppress the floating body effect without requiring complex additional components, thus maintaining device simplicity while improving reliability.
2Reliability
If multiple gate patterns are added to control the channel region potential, then the floating body effect is suppressed, but the device complexity increases
Solution Approach 1:
The patent transitions from a planar gate structure to a vertical three-dimensional structure with multiple gate patterns stacked along the vertical dimension. This allows control of the channel region at different heights, effectively suppressing the floating body effect while utilizing the vertical space efficiently.
Solution Approach 2:
Multiple gate patterns are combined in a vertical stack configuration around the semiconductor pillar. The first, second, and third gate patterns work together in unison to control the channel region, merging their functions to achieve comprehensive potential control without requiring separate complex control circuits.
3Reliability
If the semiconductor pillar uses distinct doped regions for source, channel, and drain, then the transistor performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs systematic parameter changes in the doping concentration and conductivity type across different regions of the semiconductor pillar. By gradually transitioning from the first region (first conductivity type) through the second region (second conductivity type) to the third region (first conductivity type), the patent achieves distinct functional zones with controlled boundaries, improving transistor performance while managing manufacturing precision requirements through parameter gradients.
Data Source
AI summary
Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor.