Vertical Channel Transistor Self-Aligned Gate Electrode Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices approach critical dimensions below 20 nm, the narrow gap between pillars in vertical channel transistors leads to increased gate resistance and challenges in forming thick gate electrodes without etching underlying structures, affecting data retention and performance.
Innovation Solution
The method involves forming vertical channel transistors with a double gate structure, where first gate electrodes are formed on one sidewall of pillars, and second gate electrodes are connected to the upper portions of these first gate electrodes, with shield gate electrodes functioning to minimize neighbor gate effects and reduce resistance by allowing thicker gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode is formed thin to fit the narrow gap between pillars, then the device can be integrated at critical dimensions below 20 nm, but the resistance of the gate electrode increases
Solution Approach 1:
The gate electrode structure transitions from a planar configuration to a three-dimensional configuration by forming the gate electrode to wrap around the pillar structure. This vertical channel transistor design allows the gate electrode to extend in the vertical dimension, increasing its effective cross-sectional area and reducing resistance while maintaining compatibility with the narrow horizontal gap between pillars
2Reliability
If electrodes are deposited to be thicker than a predetermined thickness to reduce resistance, then the gate resistance decreases, but it becomes difficult to separate the electrodes in the narrow gap between pillars
Solution Approach 1:
The method forms a sacrificial layer around the pillar before depositing the gate electrode material. This preliminary structure serves as a mold or template that guides the electrode formation process, allowing thick electrodes to be deposited without compromising separability. The sacrificial layer is later removed to release the electrode structure
Solution Approach 2:
A sacrificial layer acts as an intermediary structure during the electrode formation process. This temporary structure enables the deposition of thick gate electrodes by providing a form factor that maintains spacing and separability, which is then removed after the electrode is formed
3Ease of manufacture
If an over-etching process is performed to separate the electrodes, then the electrodes can be separated, but the underlying structure is etched and attacked in regions with wide gaps such as the pad region
Solution Approach 1:
The sacrificial layer is strategically designed to be present only where needed for electrode separation. By converting the potential harm of over-etching into a beneficial selective etching process, the method allows aggressive etching conditions to be used locally without damaging the underlying structure in wide gap regions, since the sacrificial layer protects those areas or is absent where protection is needed
Data Source
AI summary
A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.