Vertical Channel Transistor Gate Segmentation for Integration
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Solution Overview
Problem
Conventional semiconductor devices face challenges in increasing integration and mass production due to technical difficulties associated with manufacturing vertical channel transistors, which require new and costly exposure technologies and pose challenges different from two-dimensional transistors.
Innovation Solution
A semiconductor device with active patterns extending between intersecting trenches, featuring gate patterns with vertical electrode portions and horizontal connection portions, and a method of operating the device by applying select and unselect voltages to invert the channel region, allowing for increased integration and simplified manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel transistor is used to increase integration, then device integration is improved, but manufacturing complexity increases due to technical difficulties different from conventional transistors
Solution Approach 1:
The gate pattern is segmented into multiple vertical electrode portions disposed at different depths within the trench, allowing independent formation and control of each segment. This segmentation enables simplified manufacturing by forming gates in discrete steps rather than requiring complex single-step formation, directly resolving the manufacturing complexity issue while maintaining high integration.
Solution Approach 2:
The gate structure transitions from a conventional planar configuration to a three-dimensional vertical configuration with electrode portions at multiple depth levels. This dimensional change allows the gate to wrap around and control the channel region more effectively, achieving high integration density while simplifying the manufacturing process through vertical stacking rather than lateral expansion.
2Reliability
If gate pattern extends below lower impurity region, then channel region control is improved, but gate-induced drain leakage occurs
Solution Approach 1:
Different vertical electrode portions of the gate are positioned at specific depth locations to provide localized control over different regions of the channel. The gate structure exhibits non-uniform distribution with electrode portions strategically placed to control the channel region while avoiding extension into the drain region, thereby achieving effective channel control without inducing drain leakage.
Solution Approach 2:
The gate pattern is designed to extend below the lower impurity region to preemptively control the channel region, but the lowest electrode portion is positioned to stop before reaching the drain region. This preliminary positioning prevents the harmful gate-induced drain leakage effect from occurring in the first place, rather than attempting to correct it afterward.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased integration of semiconductor devices, simplifies manufacturing, and reduces costs by eliminating the need for additional interconnections and addressing technical difficulties such as gate-induced drain leakage, while effectively controlling the electric potential of the channel region.
Implementation Method 1
a method of operating the device by applying select and unselect voltages to invert the channel region, allowing for increased integration and simplified manufacturing
Data Source
AI summary
Provided is a semiconductor device including a substrate having active patterns extending between first trenches and between second trenches (the first and second trenches intersecting each other), and gate patterns disposed within the first trenches, wherein each of the active patterns includes lower and upper impurity regions, and a channel region between the lower and upper impurity regions, the lower and upper impurity regions being vertically spaced apart from each other and having a conductivity type different from the substrate, and the channel region having the same conductivity type as the substrate, and a bottom surface of the gate pattern is closer to a bottom surface of the first trench than the lower impurity region.