Vertical Channel Transistor Memory with Folded Bit Lines
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Solution Overview
Problem
Conventional semiconductor memory devices with open bit-line structures have large chip sizes and poor noise characteristics due to noise generated from sources other than common noise sources, which affects their performance.
Innovation Solution
A semiconductor memory device with a memory core that includes a first and second memory array block and a bit-line sense amplifier, where the word lines are positioned above and below the cell transistors, respectively, and the bit-line sense amplifier amplifies voltage differences between bit lines, optimizing the structure to reduce noise and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional open bit-line structure is used, then the memory device can be manufactured with standard processes, but the chip size becomes large and noise characteristics deteriorate
Solution Approach 1:
The patent transitions from a planar bit-line structure to a three-dimensional folded bit-line structure that extends in multiple directions (first direction and second direction perpendicular to the first). This dimensional change allows the bit lines to be folded back on themselves, significantly increasing the effective bit-line length within a compact chip area, thereby resolving the contradiction between manufacturability and chip size.
Solution Approach 2:
The memory array is divided into multiple blocks (first memory array block, second memory array block, etc.), each with its own folded bit-line structure. This segmentation allows independent optimization of each block and enables the overall chip to achieve compact size while maintaining manufacturability through modular design.
2Ease of manufacture
If a conventional open bit-line structure is used, then the manufacturing process remains standard, but noise characteristics from non-common sources deteriorate performance
Solution Approach 1:
Adjacent bit lines are merged into folded structures that share common portions. This merging creates common-mode noise paths where noise from non-common sources affects both bit lines equally, allowing the sense amplifier to reject the noise through differential signaling, thereby improving noise characteristics while maintaining standard manufacturing processes.
Solution Approach 2:
The patent converts the harmful effect of noise from non-common sources into a beneficial common-mode signal. By designing the folded bit-line structure such that external noise couples equally onto adjacent bit lines, the noise becomes a common-mode component that can be rejected by the differential sense amplifier, transforming a harmful factor into a feature that enhances noise immunity.
3Object-affected harmful factors
If word lines are positioned above and below cell transistors in a folded bit-line structure, then noise characteristics improve and chip size reduces, but device complexity increases
Solution Approach 1:
The folded bit-line structure serves multiple functions simultaneously: it reduces chip area by folding bit lines in三维 space, improves noise characteristics through common-mode noise rejection, and maintains standard manufacturing processes. This multi-functionality justifies the increased structural complexity by delivering multiple benefits from a single design approach.
Data Source
AI summary
A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.