Vertical Channel Transistor Metal Gate Fabrication
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Solution Overview
Problem
Conventional vertical channel transistors face issues with high gate resistance, poly-silicon residue bridges, over-etching, and punch phenomena due to increased integration density, which degrade transistor conductivity and stability during fabrication.
Innovation Solution
A vertical channel transistor with a metal gate structure is fabricated using active pillar patterns with a straight cylindrical shape, where a metal gate electrode is formed by interposing gate insulating layers on sidewalls, and a sacrificial layer is used to prevent over-etching and bridge formation, employing materials like Ta, Ti, TiN, TiB2, TaN, and TaSiN for the metal gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If poly-silicon gate electrode is used in conventional vertical channel transistor, then gate patterning can be performed, but gate resistance becomes high and conductivity degrades
Solution Approach 1:
The patent changes the material parameter of the gate electrode from poly-silicon to metal (such as aluminum, copper, or tungsten). This material substitution fundamentally alters the electrical conductivity parameter, reducing gate resistance by several orders of magnitude and thereby improving transistor conductivity and performance.
2Ease of manufacture
If poly-silicon layer is etched for gate patterning, then gate electrode can be formed, but poly-silicon residue accumulates to form bridges between pillar patterns
Solution Approach 1:
The patent extracts and removes the problematic poly-silicon material from the gate electrode structure and replaces it with metal. This eliminates the etching step that causes residue accumulation and bridge formation, as metal gates are formed through deposition processes that do not leave residual bridges between pillar patterns.
3Manufacturing precision
If poly-silicon layer is etched deeply to prevent bridge generation, then bridges are prevented, but lower gate oxide layer is opened and substrate is partially etched causing punch phenomenon
Solution Approach 1:
The patent removes the etching process entirely from gate formation by extracting the poly-silicon material and replacing it with metal. This eliminates the over-etching problem that leads to punch phenomenon, as metal gates are formed by deposition rather than etching, allowing precise control without compromising the gate oxide layer or substrate.
4Productivity
If integration density is increased, then memory capacity increases, but gate resistance increases and conductivity decreases
Solution Approach 1:
The patent changes the gate material parameter from poly-silicon to metal, which provides inherently lower resistance. This material substitution allows integration density to be increased while maintaining low gate resistance and high conductivity, as the metal gate's superior electrical properties compensate for the scaling effects of higher density.
Data Source
AI summary
A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.