Transistor Structure with Vertical Channel for High Resolution Panels
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Solution Overview
Problem
The complexity of panel manufacturing for electronic devices, such as display devices, leads to performance degradation and limits the reduction of transistor size, making it difficult to achieve high resolution without degrading transistor characteristics.
Innovation Solution
The electronic device incorporates a transistor structure with a short channel and high subthreshold S-parameter, allowing for increased driving margin and integration, and features a TFT array substrate with an active layer and insulating layer configuration that prevents disconnection, enabling the fabrication of ultra-high definition panels with reduced device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the degree of integration of transistors is increased to achieve high resolution, then the resolution of the electronic device is improved, but the transistor size cannot be reduced limitlessly due to process and design problems
Solution Approach 1:
The patent applies dimensionality change by forming the channel region through the third insulating layer (thickness 50-200 nm) rather than solely through planar processing. The channel length is determined by the thickness of the insulating layer, transitioning from 2D planar control to 3D vertical control, enabling shorter channel lengths without proportionally reducing transistor area.
Solution Approach 2:
The patent changes the critical parameter for channel length formation from lateral dimension to vertical dimension. By controlling the thickness of the third insulating layer (50-200 nm), the channel length is precisely controlled, allowing for shorter effective channel lengths that improve resolution while maintaining manufacturability.
2Area of stationary object
If the channel length is reduced to improve resolution, then the device area is reduced, but transistor characteristics are degraded
Solution Approach 1:
The patent resolves this contradiction by forming the channel region through the third insulating layer with controlled thickness (50-200 nm). This vertical dimension allows the channel length to be determined by thickness rather than lateral size, enabling shorter channels that reduce device area while maintaining transistor characteristics through proper thickness control.
Solution Approach 2:
The patent changes the controlling parameter from lateral channel length to vertical insulating layer thickness. By adjusting the thickness of the third insulating layer, the channel length is precisely controlled, allowing device area reduction while preserving transistor performance through optimized thickness parameters.
3Adaptability or versatility
If numerous transistors are disposed in the panel to drive various functions, then the functionality is improved, but the panel manufacturing process becomes complicated and difficult to manage
Solution Approach 1:
The patent merges multiple manufacturing steps into a single integrated process. The first, second, and third insulating layers are formed in sequence with holes punched through all layers in one etching process, and the active layer is formed in a single deposition step covering all required regions, simplifying the overall manufacturing process despite the multi-layer structure.
Solution Approach 2:
The patent performs preliminary actions by forming the first, second, and third insulating layers with integrated holes before forming the active layer. This preliminary structuring of insulating layers with predetermined hole positions enables subsequent simple active layer formation without requiring complex alignment processes, reducing manufacturing complexity.
4Ease of manufacture
If the process complexity is reduced for ease of manufacture, then the manufacturing process is simplified, but transistor performance is degraded
Solution Approach 1:
The patent combines multiple functions into a single integrated structure where the first, second, and third insulating layers with holes are formed together, and the active layer is formed in one deposition step. This merging reduces process complexity while maintaining transistor performance through precise control of layer thicknesses and hole dimensions.
Solution Approach 2:
The patent uses parameter changes in the thickness of insulating layers (first: 100-300 nm, second: 50-200 nm, third: 50-200 nm) to control channel length and transistor performance. By optimizing these thickness parameters, the patent achieves both process simplicity and high transistor performance without requiring complex manufacturing steps.
Data Source
AI summary
Provided is an electronic device. The electronic device includes at least one first transistor to which a data voltage is applied. The first transistor includes a first conductive layer disposed on a substrate and a first active layer, which is disposed on the first conductive layer, has one end and the other end which are made conductive, and includes a first channel region disposed between the one end and the other end. A second conductive layer overlapping the first conductive layer with a first insulating layer interposed between the second conductive layer and the first conductive layer is included in a storage capacitor in a panel, and the storage capacitor is disposed under the first channel region of the first active layer. In this way, an ultra-high definition panel is fabricated.