Vertical Channel Transistor Pillars for DRAM Integration
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Solution Overview
Problem
As semiconductor integration density increases, achieving smaller device areas for gigabit DRAM devices with planar MOS transistors is challenging due to the short channel effect, making it difficult to scale channel length effectively.
Innovation Solution
The development of semiconductor memory devices with semiconductor material pillars and surrounding gate electrodes, along with buried bit lines and storage node electrodes, allows for ultra-high integration density by forming vertical channel transistors with increased channel length and reduced area, using techniques like etching and dielectric film formation to create self-aligned structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar MOS transistors are used with scaled channel length, then integration density increases, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar (2D) channel structure to vertical (3D) channel structure by forming pillars extending from the substrate surface. This dimensional change allows the channel to extend vertically rather than horizontally, enabling longer effective channel length while occupying smaller planar area, thus resolving the contradiction between integration density and short channel effects
2Reliability
If channel length is increased to prevent short channel effect, then device area increases, but integration density decreases
Solution Approach 1:
By forming vertical pillars extending from the substrate, the channel length is extended in the vertical dimension rather than consuming additional planar area. The surrounding gate electrodes wrap around the pillars, providing gate control along the vertical channel length. This allows long channels to be achieved within a compact planar footprint, preventing short channel effects while maintaining small device area for high integration density
3Area of stationary object
If device area is reduced to achieve gigabit DRAM density, then manufacturing precision requirements increase
Solution Approach 1:
The patent forms the pillars and surrounding gate electrodes using preliminary photolithography and etching steps that establish self-aligned structures. The pillars are formed first, then the gate electrodes are deposited to surround them, creating inherent alignment without requiring additional high-precision alignment steps. This preliminary structuring reduces subsequent manufacturing precision requirements while achieving the small device area needed for gigabit DRAM
Data Source
AI summary
Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.