Vertical Channel Transistor with Self-Aligned Dopant Region
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Solution Overview
Problem
As integration density of semiconductor memory devices increases, particularly in DRAM, it becomes difficult to prevent short channel effects such as drain induced barrier lowering, hot carrier effect, and punch through in planar type transistors, and locating the channel region correctly during active pillar formation is challenging in vertical channel transistors.
Innovation Solution
The solution involves forming active pillars with a channel part that includes a channel dopant region on the surface, a gate electrode surrounding the outer surface of the channel part, and buried bit lines extending along columns of the pillars, with the channel dopant region being self-aligned to the channel part and the gate electrode, allowing for reduced overlap and improved alignment with source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase integration density, then the integration density is improved, but short channel effects such as drain induced barrier lowering, hot carrier effect, and punch through occur more frequently
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical channel transistor structure, changing the channel orientation from horizontal to vertical. This dimensional change allows the channel to extend through the thickness of the semiconductor layer, enabling better control over short channel effects while maintaining high integration density. The gate electrode wraps around the channel region, providing enhanced electrostatic control in the vertical dimension.
Solution Approach 2:
The gate electrode is formed to surround the channel region, with the gate oxide film positioned between the gate electrode and the channel. This nested configuration allows the gate to control the channel from multiple directions, improving electrostatic control and reducing short channel effects. The gate structure effectively encloses the channel, similar to a nested doll configuration.
2Ease of manufacture
If the channel region is defined prior to forming the active pillar, then the channel region can be formed, but it becomes difficult to locate and align the channel region with the gate electrode
Solution Approach 1:
The channel region is defined first by forming the active pillar structure with the channel dopant region, and then the gate electrode is subsequently formed to surround this pre-defined channel region. This preliminary definition of the channel region allows for better control and alignment, as the gate electrode can be precisely positioned relative to the already-formed channel structure.
Solution Approach 2:
The active pillar structure serves as a self-aligning feature for the gate electrode formation. The channel dopant region within the active pillar automatically defines the channel location, and the subsequent gate electrode formation process naturally aligns to this pre-defined structure, reducing the need for additional alignment steps and improving manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively limits or prevents short channel effects, enhances channel current by fully depleting the channel part, and reduces aligning errors between the gate electrode and channel dopant region, improving the performance of vertical channel transistors.
Implementation Method 1
Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part
Data Source
AI summary
Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.