Vertical Channel Transistor Stack for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor technologies face challenges in miniaturizing electronic products while maintaining performance and reducing parasitic capacitance, which affects the size and efficiency of transistors and other electronic components.
Innovation Solution
A semiconductor device is fabricated using a stacked structure with horizontal gate structures and channel layers, where the channel layers are formed on either side of the stacked structures, and electrode layers are used to reduce parasitic capacitance and improve operation characteristics by minimizing the distance between channel layers and optimizing doping processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar transistor structures are used, then manufacturing is simpler, but device area is larger and parasitic capacitance is higher
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked structure. Multiple transistor components (gate electrodes, channel layers, electrode layers) are arranged vertically in stacked configurations, allowing higher integration density within the same footprint area while reducing parasitic capacitance through improved spatial separation
2Area of stationary object
If transistor size is reduced for miniaturization, then integration density improves, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
By stacking transistor components vertically, the patent reduces the horizontal footprint while maintaining electrical performance. The vertical arrangement allows better control of parasitic capacitance through optimized spacing and positioning of conductive elements in the third dimension
Solution Approach 2:
The transistor structure is divided into multiple discrete stacked layers including first and second gate electrodes, channel layers, and electrode layers. This segmentation allows independent optimization of each layer's dimensions and positioning to minimize parasitic effects while maintaining functionality
3Adaptability or versatility
If more transistor components are integrated in planar layout, then functionality improves, but device area increases
Solution Approach 1:
The patent employs vertical stacking to integrate multiple transistor components (source/drain electrodes, gate structures, channel layers) within a compact three-dimensional volume. This approach achieves high functionality without proportionally increasing the horizontal device area, enabling better integration density
Data Source
AI summary
A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.