Vertical-Channel Semiconductor Device Stacking for Dense Reliable Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration, miniaturization, high on-state current, favorable electrical characteristics, and high reliability while maintaining high productivity and density of transistors, particularly for applications in high-resolution display apparatuses like VR, AR, and MR.
Innovation Solution
A semiconductor device design incorporating a first and second transistor configuration with specific conductive and insulating layers, where the transistors are electrically connected, and a manufacturing method involving the formation of conductive and semiconductor layers with precise alignment and oxygen treatment to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are miniaturized to increase integration density, then the degree of integration is improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent introduces a vertical channel structure where the channel extends in the thickness direction rather than solely in the plane. This three-dimensional configuration allows increased integration density without proportionally decreasing manufacturing precision, as the critical dimensions are distributed across multiple vertical layers rather than compressed in a single plane.
Solution Approach 2:
The transistor structure is divided into multiple segments: first and second semiconductor layers, first and second conductive layers, and first and second insulating layers. This segmentation allows each component to be optimized and manufactured with standard precision, while the overall device achieves miniaturization through the stacked configuration of these segments.
2Quantity of substance
If transistors are miniaturized to increase integration density, then the degree of integration is improved, but device reliability becomes more difficult to maintain
Solution Approach 1:
The patent employs composite material structures combining different semiconductor layers (first and second semiconductor layers with different materials or compositions), insulating layers, and conductive layers. This composite approach allows optimization of reliability for each layer while maintaining overall miniaturization and high integration density.
Solution Approach 2:
By transitioning to a vertical channel architecture, the patent distributes stress and improves heat dissipation pathways in the thickness direction, thereby enhancing device reliability while achieving high integration density through three-dimensional packing rather than two-dimensional scaling.
3Productivity
If transistor structure is simplified to improve productivity, then manufacturing efficiency is improved, but electrical characteristics and on-state current become insufficient
Solution Approach 1:
The vertical channel structure increases the effective channel area in the thickness direction, thereby increasing on-state current without requiring proportional increases in planar area. This maintains manufacturing efficiency while improving power output.
Solution Approach 2:
The patent combines multiple functional elements into integrated stacked structures where conductive layers, semiconductor layers, and insulating layers are merged in a vertical sequence. This merging enables simultaneous achievement of high on-state current, favorable electrical characteristics, and manufacturing efficiency through a unified fabrication process.
4Quantity of substance
If conductive layers are densely packed to increase transistor density, then integration is improved, but alignment precision becomes more difficult to maintain
Solution Approach 1:
The patent arranges conductive layers in the vertical dimension rather than solely in the planar dimension. This three-dimensional stacking achieves high transistor density while reducing the alignment precision requirements that would otherwise apply to densely packed lateral structures.
Solution Approach 2:
The conductive layers, semiconductor layers, and insulating layers are nested within each other in a stacked configuration. This nested structure enables high integration density while maintaining alignment precision, as each layer is positioned relative to the layers beneath it rather than requiring precise lateral alignment with adjacent layers.
Data Source
AI summary
A semiconductor device having a high degree of integration is provided. A first and second transistors which are electrically connected to each other and a first insulating layer are included. The first transistor includes a first semiconductor layer, a second insulating layer, and a first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and a fourth to sixth conductive layers. The first insulating layer is positioned over the first conductive layer and includes an opening reaching the first conductive layer. The second conductive layer is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer is positioned over the second insulating layer to overlap with the inner wall of the opening. The third insulating layer is positioned over the fourth conductive layer. The fifth and sixth conductive layers are positioned over the fourth conductive layer with the third insulating layer therebetween. The second semiconductor layer is in contact with top surfaces of the fifth and sixth conductive layers, side surfaces thereof that face each other, and a top surface of the third insulating layer sandwiched between the fifth conductive layer and the sixth conductive layer.