Vertical-Channel Transistor Structure for High-Resolution Displays
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Solution Overview
Problem
The challenge of miniaturizing transistors to achieve high-resolution display devices, particularly for applications in virtual and augmented reality, is hindered by conventional transistor designs that occupy large areas and have high wiring resistance, limiting the ability to reduce pixel size and enhance display resolution.
Innovation Solution
A novel transistor structure is introduced, featuring a semiconductor layer in contact with a side surface of an insulating layer, with a gate insulating layer and gate electrode positioned to facilitate a vertical channel configuration, allowing for a reduced channel length and area occupation, and incorporating a conductive layer with increased thickness to minimize wiring resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional transistor designs are used, then manufacturing is simpler, but the transistor area is large and channel length is long
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical channel structure by having the semiconductor layer contact the side surface of the insulating layer rather than only the top surface. This dimensional change allows the channel to extend vertically, reducing the planar area occupied by the transistor while maintaining functional channel length, thereby resolving the contradiction between minimizing transistor area and managing structural complexity.
Solution Approach 2:
The patent employs a nested configuration where the gate electrode is positioned within a recess formed in the insulating layer, and the semiconductor layer is embedded within the insulating layer structure. This nesting arrangement allows multiple components to occupy overlapping spatial regions, reducing the overall footprint of the transistor while maintaining proper electrical isolation and connectivity, thus addressing the area-complexity tradeoff.
2Reliability
If conventional transistor designs are used, then wiring resistance is high, but manufacturing is simpler
Solution Approach 1:
The patent introduces a thick first conductive layer that contacts the gate electrode and extends in the planar direction, creating a low-resistance wiring path. This conductive layer is positioned at a different vertical level than conventional designs, forming a three-dimensional wiring structure that reduces resistance by increasing the cross-sectional area of current flow paths without simply scaling up planar dimensions, thus improving reliability while managing complexity through vertical integration.
3Length of moving object
If transistor channel length is reduced, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By forming the channel vertically along the side surface of the insulating layer, the patent decouples channel length control from planar alignment requirements. The channel length is determined primarily by the height of the insulating layer's side surface, which can be controlled through deposition thickness rather than requiring precise lateral alignment during fabrication. This vertical configuration reduces sensitivity to alignment errors while achieving short channel lengths, thereby resolving the contradiction between miniaturization and manufacturing precision.
Data Source
AI summary
A transistor that can be miniaturized is provided. A transistor that occupies a small area is provided. A transistor with a small channel length is provided. A semiconductor device includes a first insulating layer, a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, a second electrode, and a first conductive layer. A side surface of the first insulating layer is positioned over the first electrode. The second electrode is positioned over the first insulating layer. The semiconductor layer is in contact with the first electrode, the side surface of the first insulating layer, and the second electrode. The gate insulating layer includes a portion facing the side surface with the semiconductor layer therebetween. The gate electrode includes a portion facing the side surface with the gate insulating layer and the semiconductor layer therebetween. The first conductive layer is in contact with the gate electrode, includes a portion facing the side surface with the gate electrode, the gate insulating layer, and the semiconductor layer therebetween, and includes a portion thicker than the gate electrode.