Vertical Channel Transistors for High Integration Density
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the need for new exposure techniques and high costs associated with reducing line widths, and existing transistors occupy significant planar areas, hindering further miniaturization.
Innovation Solution
The fabrication method involves forming vertical transistors with buried dielectric patterns and gate structures, allowing for the creation of active pillars and interconnections that reduce the footprint of transistors while maintaining electrical connectivity, using techniques such as oxidation processes and sacrificial spacers to define fin patterns and form trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If line widths are reduced to increase integration density, then integration density is improved, but new exposure techniques and high costs are required
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, utilizing the third dimension (vertical stacking of source and drain) to increase integration density without reducing line widths. This dimensional change allows more transistors to be packed into the same planar area, improving integration density while avoiding the need for expensive new exposure techniques
2Quantity of substance
If line widths are reduced to increase integration density, then integration density is improved, but new exposure techniques are required
Solution Approach 1:
By stacking source and drain vertically to form vertical channel transistors, the patent increases the number of transistors per unit area without requiring reduction of line widths. This approach maintains compatibility with existing exposure techniques while achieving higher integration density through vertical architecture
3Ease of manufacture
If planar transistors are used, then fabrication is simpler, but transistor footprint is large
Solution Approach 1:
The patent employs vertical channel transistors where source and drain are stacked vertically, reducing the planar footprint of each transistor while maintaining fabrication processes that are substantially similar to conventional planar transistors. The vertical architecture allows transistors to occupy less planar area without significantly complicating the fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased integration density and reduced transistor size without the need for expensive new exposure techniques, allowing for more compact and efficient semiconductor devices.
Implementation Method 1
applying an oxidation process to the substrate having the lower trenches to form the buried dielectric patterns
Data Source
AI summary
Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.