Vertical Channel Semiconductor Structure for Wider Channels
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Solution Overview
Problem
As semiconductor devices are scaled down, their operation characteristics deteriorate due to high-integration limitations, necessitating improved performance and electrical characteristics.
Innovation Solution
The implementation of vertical channel transistors with increased channel width and specific structural configurations, including mold structures and semiconductor patterns, enhances electrical performance by increasing channel area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal-oxide-semiconductor field effect transistors are scaled down to achieve higher integration, then device density increases, but operation characteristics deteriorate
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, changing the dimensional orientation of the channel from 2D to 3D. This vertical configuration increases the channel width and effective area without increasing the footprint on the substrate, thereby maintaining high integration density while improving operation characteristics through enhanced carrier transport and reduced resistance.
Solution Approach 2:
The patent modifies key geometric parameters of the transistor structure, specifically increasing the channel width and adjusting the mold structure dimensions. By changing these physical parameters, the device achieves improved electrical characteristics and operation performance while maintaining the scaled-down form factor required for high integration.
2Reliability
If channel width is increased to improve electrical characteristics, then electrical performance improves, but device area increases
Solution Approach 1:
The vertical channel structure allows the channel width to extend in the vertical dimension rather than horizontally. This enables increased channel width and improved electrical characteristics without proportionally increasing the lateral device area, as the expanded channel dimension is achieved through vertical stacking rather than horizontal expansion.
3Reliability
If contact resistance is reduced to improve operation characteristics, then electrical performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates contact resistance reduction measures into the preliminary manufacturing steps, such as optimizing the mold structure design and semiconductor pattern formation during the fabrication process. By addressing contact resistance early in the manufacturing sequence rather than as a separate correction step, the patent reduces overall manufacturing complexity while achieving improved electrical performance.
Data Source
AI summary
A semiconductor device includes a bit line extending in a first direction, a mold structure extending in a second direction and having a first side surface and a second side surface opposed to each other in the first direction, and a first vertical semiconductor pattern and a second vertical semiconductor pattern that are on the bit line and are respectively on the first side surface and the second side surface of the mold structure. Each of the first side surface and the second side surface of the mold structure has a nonlinear portion, and the first vertical semiconductor pattern extends along the nonlinear portion of the first side surface, and the second vertical semiconductor pattern extends along the nonlinear portion of the second side surface.