Vertical Channel Memory Cell Layout With Shorter Word Line Path
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and improving operation speed and production yield as they are scaled down, particularly in maintaining effective electrical characteristics and resistance with vertical channel transistors.
Innovation Solution
A semiconductor device design that includes a substrate with first and second transistors, a bit line connected to the first transistor, a channel layer, a gate insulating layer, a word line, a landing pad connected to the channel layer, and a connection pad connected to the word line, with a division structure separating the landing and connection pads, which reduces the electrical conduction path length between the word line and the second transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are scaled down to increase integration density, then the number of devices per unit area increases, but the electrical characteristics and resistance of transistors deteriorate
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, utilizing the vertical dimension to maintain effective channel length and electrical characteristics while increasing integration density in the horizontal plane. The vertical channel structure allows current to flow perpendicular to the substrate surface, enabling higher device density without sacrificing transistor performance.
Solution Approach 2:
The patent divides the transistor structure into distinct vertical segments including source region, channel region, and drain region arranged vertically. This segmentation allows each region to be optimized independently for its specific function while maintaining compact horizontal footprint, thereby improving integration density without compromising electrical characteristics.
2Ease of manufacture
If conventional pad structures are used in vertical channel transistor devices, then manufacturing is simplified, but the conduction path length remains excessive affecting electrical characteristics
Solution Approach 1:
The patent introduces a division structure comprising a first division pattern and second division pattern that act as intermediary conductive elements between the source/drain regions and the source/drain electrodes. These intermediate structures reduce the conduction path length by providing direct vertical contact paths, thereby improving electrical characteristics while maintaining manufacturing feasibility through standard patterning processes.
3Speed
If the conduction path length between word line and transistor is reduced to improve operation speed, then signal transmission speed increases, but the device layout becomes more complex
Solution Approach 1:
The patent utilizes vertical stacking to reduce the horizontal layout footprint and conduction path length. By arranging the channel layer, gate insulating layer, and word line in vertical layers, the design achieves shorter electrical paths and faster signal transmission without increasing planar complexity, as the vertical dimension handles the additional structural requirements.
Data Source
AI summary
A semiconductor device includes a substrate, a first transistor and a second transistor on the substrate, a bit line electrically connected to the first transistor, a channel layer on the bit line, a gate insulating layer on the channel layer, a word line on the gate insulating layer, a landing pad electrically connected to the channel layer, a connection pad electrically connected to the word line and the second transistor, and a division structure separating the landing pad from the connection pad. The division structure includes an intervening portion between the landing pad and the connection pad.