Self-Aligned Vertical Semiconductor Channels for Continuous Gate Length
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices, such as vertical nanosheet or nanowire FETs, face challenges in achieving continuous gate lengths, which are necessary for input/output and analog devices, and current manufacturing methods lack effective control over short channel effects.
Innovation Solution
A vertical semiconductor device with a continuous gate length is manufactured by forming self-aligned vertical channel portions on a substrate, using epitaxial growth to define the channel layers, and a gate stack is formed to surround these channels, ensuring consistent gate lengths through precise etching and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If vertical nanosheet or nanowire FET structures are used, then device miniaturization is achieved, but continuous gate length cannot be obtained
Solution Approach 1:
The channel is divided into multiple vertical nanosheet or nanowire segments stacked vertically, with each segment forming a portion of the continuous channel. The gate wraps around each segment, creating a segmented structure that achieves continuous gate length through vertical stacking rather than lateral extension.
Solution Approach 2:
The invention transitions from lateral channel extension to vertical channel stacking, utilizing the vertical dimension to achieve continuous gate length. Multiple channel segments are stacked vertically with gates wrapping around each segment, converting a 2D lateral problem into a 3D vertical solution.
2Productivity
If vertical channel structures are used, then device integration density is improved, but control over short channel effects deteriorates
Solution Approach 1:
The gate structure is nested around each vertical channel segment in a wrap-around configuration, with multiple such nested structures stacked vertically. This nested arrangement provides comprehensive gate control over each channel segment while maintaining vertical integration for high density.
Solution Approach 2:
The invention changes the geometric parameters of the channel structure by vertical stacking and adjusts the gate configuration to wrap around each segment. This parameter change from lateral to vertical orientation, combined with wrap-around gating, improves short channel effect control while maintaining integration density.
3Ease of manufacture
If conventional manufacturing processes are used, then manufacturing simplicity is maintained, but manufacturing precision of gate length deteriorates
Solution Approach 1:
Channel segments and gate structures are formed in predetermined stacked configurations using sequential deposition and etching steps. Position retaining layers are formed in advance to define precise channel positions before final gate formation, ensuring accurate gate length control through pre-planned structural arrangement.
Solution Approach 2:
Position retaining layers serve as intermediary structures that define and maintain precise channel positions during manufacturing. These intermediary layers enable accurate gate length control by providing reference structures for subsequent processing steps without requiring complex direct patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor device with controlled short channel effects and continuous gate lengths, enhancing device performance and reliability.
Implementation Method 1
forming a channel layer on a surface of the second material layer exposed by the first recess portion
Data Source
AI summary
A vertical semiconductor device with a continuous gate length and a method of manufacturing the same, and an electronic apparatus including the same. The semiconductor device includes: a semiconductor base on a substrate; first and second vertical channel portions on the semiconductor base, where the first and second vertical channel portions are vertical relative to the substrate, protrude from the semiconductor base, are spaced apart from in a first direction and self-aligned with each other, and the semiconductor base extends continuously between the first and second vertical channel portions; a first source/drain portion and a second source/drain portion on the first vertical channel portion and the second vertical channel portion, respectively; and a gate stack at least partially on the first vertical channel portion, the semiconductor base, and the second vertical channel portion to define a continuous channel between the first source/drain portion and the second source/drain portion.