Vertical Charge Storage Layers to Inhibit Charge Spreading
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Solution Overview
Problem
Semiconductor devices with conventional planar transistor structures face limitations in increasing integration density and reliability, particularly in maintaining electrical characteristics and preventing charge spreading.
Innovation Solution
A semiconductor device with vertical transistor structures, featuring gate electrodes stacked perpendicularly on a substrate, interlayer insulating layers, channel structures including tunneling and charge storage layers, and blocking insulating layers, which are designed to enhance integration and reliability by optimizing the arrangement and manufacturing process of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar transistor structures are used, then manufacturing process is simple, but integration density cannot be increased
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to vertical (3D) transistor structures by stacking gate electrodes, channel structures, and interlayer insulating layers in the vertical direction. This dimensional change enables increased integration density while maintaining manufacturability through adapted fabrication processes.
2Quantity of substance
If charge storage layers are added to increase integration density, then more data can be stored, but charge spreading occurs reducing reliability
Solution Approach 1:
The patent divides the charge storage functionality into multiple separate charge storage layers (first charge storage layer and second charge storage layer) stacked vertically. Each layer is independently surrounded by blocking insulating layers, which segment and isolate the charge storage regions. This segmentation prevents charge spreading between layers while maintaining high storage capacity.
Solution Approach 2:
The patent introduces blocking insulating layers as intermediary structures between the charge storage layers and between the charge storage layers and channel structures. These blocking insulating layers act as mediators that prevent charge spreading while allowing the charge storage layers to function independently, thus maintaining reliability while increasing storage capacity.
3Quantity of substance
If vertical transistor structures are implemented, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the vertical structure into distinct functional layers (gate electrodes, interlayer insulating layers, channel structures, tunneling insulating layers, charge storage layers, blocking insulating layers) that can be formed through sequential deposition and etching processes. This segmentation enables controlled fabrication of complex vertical structures while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device achieves improved reliability and integration density by inhibiting charge spreading and maintaining electrical characteristics through the strategic arrangement of charge storage layers and blocking insulating layers, thereby enhancing the performance and capacity of semiconductor devices.
Implementation Method 1
a tunneling insulating layer on the channel layer and extending perpendicularly to the upper surface of the substrate
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.