Vertical Semiconductor Chip Package Stacking for Signal Speed
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Solution Overview
Problem
The existing semiconductor chip packaging methods result in increased module size and complexity due to horizontal arrangement of chips, which hinders high-speed signal transmission and complicates manufacturing, especially in portable devices requiring thin and lightweight designs.
Innovation Solution
A semiconductor chip package design featuring vertically stacked chip packages with an insulation frame, conductive parts, inner insulation layers, and signal patterns, allowing for reduced module size and enhanced signal processing speed by eliminating the need for a substrate and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chip packages are horizontally mounted on a substrate, then signal transmission between chips is enabled, but the substrate area increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from horizontal arrangement of semiconductor chip packages on a substrate to vertical stacking of chip packages. This dimensional change eliminates the need for a large substrate area while maintaining signal transmission capabilities through direct vertical connections between stacked chips.
Solution Approach 2:
The invention extracts and eliminates the substrate from the traditional horizontal mounting structure. By removing the substrate requirement, the patent achieves compact vertical stacking of chip packages, thereby reducing the overall area while preserving electrical connectivity through direct chip-to-chip connections.
2Reliability
If multiple semiconductor chip packages are horizontally mounted on a substrate, then signal transmission between chips is enabled, but the manufacturing process becomes complicated
Solution Approach 1:
By stacking chip packages vertically instead of arranging them horizontally on a substrate, the patent simplifies the manufacturing process. The vertical stacking approach eliminates complex substrate wiring and assembly steps, reducing manufacturing complexity while maintaining signal transmission functionality.
3Reliability
If multiple semiconductor chip packages are horizontally mounted on a substrate, then signal transmission between chips is enabled, but the signal transmission distance increases
Solution Approach 1:
The patent reduces signal transmission distance by arranging chip packages in a vertical stack rather than spreading them horizontally. This vertical configuration minimizes the physical distance between chips, enabling shorter signal paths and improving transmission performance.
4Reliability
If semiconductor components are arranged horizontally on a substrate, then electrical connection between components is achieved, but the module size and weight increase
Solution Approach 1:
The invention achieves electrical connection between semiconductor components through vertical stacking of chip packages, eliminating the need for a large horizontal substrate. This three-dimensional arrangement maintains all necessary electrical connections while dramatically reducing the overall module size and weight.
5Reliability
If multiple layers of metal wiring are formed on a PCB substrate for high-performance signal transmission, then signal transmission quality is improved, but the manufacturing process becomes more complicated and costs increase
Solution Approach 1:
The patent extracts and eliminates the multi-layer metal wiring structure from the PCB substrate. By removing the substrate entirely and adopting vertical chip stacking, the invention achieves high-performance signal transmission through direct chip connections, thereby simplifying the manufacturing process and reducing costs.
Data Source
AI summary
In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.