Vertical Chip Packaging via Mother Substrate Interconnecting Bumps
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Solution Overview
Problem
Current chip packaging technologies face limitations in area utilization and signal quality due to the need for extensive interconnecting paths through multiple substrates, leading to restricted placement and increased signal loss.
Innovation Solution
A packaging method that forms plated through holes directly on a substrate to connect wiring layers on opposite surfaces, allowing chips to be placed on daughter carrier substrates with reduced signal path length and enhanced signal quality by integrating connections within a single daughter carrier substrate, using mother substrate interconnecting bumps for external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If daughter carrier substrates are placed side by side on the mother carrier substrate, then electrical connections between chips are achieved, but the area of the mother carrier substrate cannot be further reduced
Solution Approach 1:
The patent transitions from horizontal placement of daughter substrates on the mother substrate to vertical stacking, where daughter substrates are arranged in layers above and below the mother substrate. This three-dimensional arrangement allows electrical connections to be achieved through vertical plated through holes rather than extensive horizontal wiring, significantly reducing the area occupied on the mother carrier substrate while maintaining connection reliability.
2Reliability
If interconnecting paths go through multiple plated through holes among wiring layers, then electrical connections are established, but signal loss increases due to reflections
Solution Approach 1:
The patent reduces the number of horizontal wiring layers and plated through holes by transitioning to a vertical stacking architecture. Signals travel through fewer interfaces and plated through holes in the vertical arrangement, minimizing reflections and signal loss compared to the traditional multi-layer horizontal interconnection approach.
3Reliability
If interconnecting wires are placed right between daughter carrier substrates, then signal quality is maintained, but placement area and number of interconnecting wires are restricted
Solution Approach 1:
The vertical stacking architecture frees the mother substrate from the constraint of placing interconnecting wires only between daughter substrates. The mother substrate can now be utilized more flexibly for additional functional elements, I/O connections, and routing, as the primary interconnections between chips are established through the vertical plated through holes in the stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly shortens signal paths and reduces the number of solder joints, enhancing signal quality and allowing for more efficient use of the mother carrier substrate area by minimizing the need for extensive horizontal wiring on the mother substrate.
Implementation Method 1
connecting the first wiring layer electrically with the second wiring layer through the plated through holes
Implementation Method 2
configuring a solder layer on a lateral face of the mother substrate interconnecting bump
Data Source
AI summary
A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.