Vertical Clock Delivery Architecture for Dense Chip Routing
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Solution Overview
Problem
Conventional computing systems face limitations in computing density and performance due to significant space requirements for power and clock signal routing, which results in long delivery paths leading to power loss, jitter, and noise interference.
Innovation Solution
Implementing a vertical clock delivery architecture where power and clock signals are provided orthogonally to chips, using vertically positioned power delivery modules with integrated crystal oscillators, and employing differential signaling with electrical isolation to reduce noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional horizontal routing is used for power and clock signals, then routing can be implemented using standard PCB layout, but significant space is consumed and long delivery paths cause power loss and jitter
Solution Approach 1:
The patent transitions from conventional horizontal routing on the PCB surface to vertical routing through the PCB thickness. Power and clock signals are delivered via vias that extend vertically from the bottom surface through the substrate to the top surface, where they connect to the chip. This dimensional change significantly shortens the signal delivery path length, reducing power loss and jitter while maintaining routing functionality.
2Productivity
If more chips are packed to increase computing density, then performance improves, but routing space for power and clock signals becomes insufficient
Solution Approach 1:
By moving power and clock signal routing from the horizontal plane to the vertical dimension through the PCB substrate, the invention eliminates the competition for planar routing space between signal paths and chip placements. This allows chips to be packed more densely on the PCB surface without compromising routing availability, thereby increasing computing density.
Solution Approach 2:
The power delivery module is integrated with the clock signal generation functionality, combining multiple functions into a single compact unit that can be positioned adjacent to each chip. This merging reduces the total area required for separate power and clock routing infrastructure, enabling higher chip density.
3Reliability
If clock signals are delivered through long horizontal paths, then routing is simpler, but noise interference and jitter increase
Solution Approach 1:
The patent implements vertical signal delivery through the PCB substrate using vias, which dramatically reduces the horizontal path length. The clock signals travel vertically from the bottom surface through the substrate thickness to the chip, minimizing the exposure to noise and reducing cumulative jitter compared to long horizontal traces.
Solution Approach 2:
The PCB substrate acts as an intermediary medium that facilitates vertical signal transmission. The substrate provides a controlled environment for vertical vias, shielding the short vertical path from external noise while maintaining signal integrity. This intermediary structure enables reliable clock delivery over minimal distances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power loss, jitter, and noise interference, enabling higher computing density and performance, particularly suitable for AI machine learning applications.
Implementation Method 1
the power delivery module includes at least one crystal oscillator to generate the one or more clock signals
Data Source
AI summary
Systems and methods of for vertical power and clock delivery are disclosed. In some embodiments, a computing system can include an array of chips comprising a chip and a power delivery module configured to provide a power supply voltage and one or more clock signals to the chip, the power delivery module being positioned vertically relative to the chip, and the chip configured to vertically receive the one or more clock signals from the power delivery module.